Patents by Inventor Cheng-Chung Lin
Cheng-Chung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120088362Abstract: A method includes allowing a work piece having a solder bump to contact a bond head; heating the bond head until the solder bump is melted; and conducting a cooling media into the bond head to cool the solder bump and to solidify the solder bump.Type: ApplicationFiled: October 8, 2010Publication date: April 12, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien Ling Hwang, Cheng-Chung Lin, Ying-Jui Huang, Chung-Shi Liu
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Publication number: 20120049346Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.Type: ApplicationFiled: August 30, 2010Publication date: March 1, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Chung Lin, Chung-Shi Liu, Meng-Wei Chou, Kuo Cheng Lin, Wen-Hsiung Lu, Chien Ling Hwang, Ying-Jui Huang, De-Yuan Lu
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Publication number: 20120038466Abstract: A picking system comprises a radio frequency identification (RFID) tag, a case, a two-wire conductive strip, at least one identifying unit and a processing unit. The two-wire conductive strip is electrically connected between the identifying unit and the processing unit. The identifying unit reads tag information within the RFID tag for actively and instantly controlling the authorization of an operating staff assigned for particular items thereby improving the accuracy of picking items.Type: ApplicationFiled: January 6, 2011Publication date: February 16, 2012Inventors: Chun-Hui HUANG, Hsien-Min Hsu, Cheng-Chung Lin, Chih-Lung Liu
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Patent number: 8104666Abstract: A method of bonding includes providing a first work piece, and attaching a second work piece on the first work piece, with a solder bump disposed between the first and the second work pieces. The second work piece is heated using a heating head of a heating tool to melt the solder bump. After the step of heating the second work piece, one of the first and the second work pieces is allowed to move freely in a horizontal direction to self-align the first and the second work pieces. After the step of allowing one of the first and the second work pieces to move, a temperature of the heating head is lowed until the first solder bump solidifies to form a second solder bump.Type: GrantFiled: September 1, 2010Date of Patent: January 31, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien Ling Hwang, Ying-Jui Huang, Cheng-Chung Lin, Chung-Shi Liu
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Publication number: 20120018878Abstract: A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.Type: ApplicationFiled: July 26, 2010Publication date: January 26, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Da Cheng, MIng-Che Ho, Chung-Shi Liu, Chien Ling Hwang, Cheng-Chung Lin, Hui-Jung Tsai, Zheng-Yi Lim
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Publication number: 20120007230Abstract: An embodiment of the disclosure includes a conductive bump on a semiconductor die. A substrate is provided. A bond pad is over the substrate. An under bump metallurgy (UBM) layer is over the bond pad. A copper pillar is over the UBM layer. The copper pillar has a top surface with a first width and sidewalls with a concave shape. A nickel layer having a top surface and a bottom surface is over the top surface of the copper pillar. The bottom surface of the nickel layer has a second width. A ratio of the second width to the first width is between about 0.93 to about 1.07. A solder material is over the top surface of the cap layer.Type: ApplicationFiled: July 8, 2010Publication date: January 12, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien Ling Hwang, Ying-Jui Huang, Zheng-Yi Lim, Yi-Yang Lei, Cheng-Chung Lin, Chung-Shi Liu
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Patent number: 8053894Abstract: Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.Type: GrantFiled: August 26, 2005Date of Patent: November 8, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Kai Wan, Yih-Hsiung Lin, Ming-Ta Lei, Baw-Ching Perng, Cheng-Chung Lin, Chia-Hui Lin, Ai-Sen Liu
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Publication number: 20110266667Abstract: A sidewall protection structure is provided for covering at least a portion of a sidewall surface of a bump structure, in which a protection structure on the sidewalls of a Cu pillar and a surface region of an under-bump-metallurgy (UBM) layer is formed of at least one non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof.Type: ApplicationFiled: April 29, 2010Publication date: November 3, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Wen WU, Cheng-Chung LIN, Chien Ling HWANG, Chung-Shi LIU
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Publication number: 20110133331Abstract: An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface.Type: ApplicationFiled: December 8, 2009Publication date: June 9, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Chung Lin, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20110092064Abstract: A method of forming an integrated circuit structure includes forming a copper-containing seed layer on a wafer, and performing a descum step on an exposed surface of the copper-containing seed layer. The descum step is performed using a process gas including fluorine and oxygen. A reduction/purge step is then performed on the exposed surface of the copper-containing seed layer using a nitrogen-containing gas. A copper-containing layer is plated on the copper-containing seed layer.Type: ApplicationFiled: July 23, 2010Publication date: April 21, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Shi Liu, Cheng-Chung Lin, Ming-Che Ho, Kuo Cheng Lin, Meng-Wei Chou
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Publication number: 20100201490Abstract: A display device includes a RFID tag unit, a display unit, a processing unit and a power supply unit. The RFID tag unit follows a wireless communication standard of a RFID system to receive a wireless signal and outputs identification information. The processing unit electrically connected with the RFID tag unit and the display unit receives the identification information and outputs to the display unit for displaying. The power supply unit supplies operation power required to the processing unit and the display unit. The required power while the above-mentioned display device refreshes the information is supplied by the power supply unit, so that the information can be refreshed with longer communication distance and power saving is achieved. A display system including the above-mentioned display device and a reader/writer device is also disclosed.Type: ApplicationFiled: March 16, 2009Publication date: August 12, 2010Inventors: Chun-Hui Huang, Cheng-Chung Lin, Kuo-Yuan Tseng
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Patent number: 7271103Abstract: A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.Type: GrantFiled: October 17, 2003Date of Patent: September 18, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuei-Wu Huang, Ai-Sen Liu, Baw-Ching Perng, Ming-Ta Lei, Wen-Kai Wan, Cheng-Chung Lin, Yih-Shung Lin, Chia-Hui Lin
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Patent number: 7176137Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.Type: GrantFiled: May 9, 2003Date of Patent: February 13, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Baw-Ching Perng, Yih-Shung Lin, Ming-Ta Lei, Ai-Sen Liu, Chia-Hui Lin, Cheng-Chung Lin
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Publication number: 20060113616Abstract: A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.Type: ApplicationFiled: August 18, 2005Publication date: June 1, 2006Inventors: Ai-Sen Liu, Baw-Ching Perng, Ming-Ta Lei, Yih-Shung Lin, Cheng-Chung Lin, Chia-Hui Lin
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Patent number: 7011929Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.Type: GrantFiled: January 9, 2003Date of Patent: March 14, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Ta Lei, Yih-Shung Lin, Ai-Sen Liu, Cheng-Chung Lin, Baw-Ching Perng, Chia-Hui Lin
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Publication number: 20060001160Abstract: Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.Type: ApplicationFiled: August 26, 2005Publication date: January 5, 2006Inventors: Wen-Kai Wan, Yih-Hsiung Lin, Ming-Ta Lei, Baw-Ching Perng, Cheng-Chung Lin, Chia-Hui Lin, Ai-Sen Liu
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Patent number: 6955984Abstract: Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.Type: GrantFiled: May 16, 2003Date of Patent: October 18, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Kai Wan, Yih-Hsiung Lin, Ming-Dai Lei, Baw-Ching Perng, Cheng-Chung Lin, Chia-Hui Lin, Ai-Sen Liu
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Patent number: 6943077Abstract: A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.Type: GrantFiled: April 7, 2003Date of Patent: September 13, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ai-Sen Liu, Baw-Ching Perng, Ming-Ta Lei, Yih-Shung Lin, Cheng-Chung Lin, Chia-Hui Lin
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Publication number: 20050085083Abstract: A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.Type: ApplicationFiled: October 17, 2003Publication date: April 21, 2005Inventors: Kuei-Wu Huang, Ai-Sen Liu, Baw-Ching Perng, Ming-Ta Lei, Wen-Kai Wan, Cheng-Chung Lin, Yih-Shung Lin, Chia-Hui Lin
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Publication number: 20040229460Abstract: Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.Type: ApplicationFiled: May 16, 2003Publication date: November 18, 2004Inventors: Wen-Kai Wan, Yih-Hsiung Lin, Ming-Ta Lei, Baw-Ching Perng, Cheng-Chung Lin, Chia-Hui Lin, Ai-Sen Liu