Patents by Inventor Cheng-Hsiung Tsai

Cheng-Hsiung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12228395
    Abstract: Methods and apparatus for substrate position calibration for substrate supports in substrate processing systems are provided herein. In some embodiments, a method for positioning a substrate on a substrate support includes: obtaining a plurality of backside pressure values corresponding to a plurality of different substrate positions on a substrate support by repeatedly placing a substrate in a position on the substrate support, and vacuum chucking the substrate to the substrate support and measuring a backside pressure; and analyzing the plurality of backside pressure values to determine a calibrated substrate position.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: February 18, 2025
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tomoharu Matsushita, Aravind Kamath, Jallepally Ravi, Cheng-Hsiung Tsai, Hiroyuki Takahama
  • Patent number: 12165920
    Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hwei-Jay Chu, Chieh-Han Wu, Cheng-Hsiung Tsai, Chung-Ju Lee
  • Publication number: 20240379437
    Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: HWEI-JAY CHU, CHIEH-HAN WU, CHENG-HSIUNG TSAI, CHUNG-JU LEE
  • Publication number: 20240339396
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Application
    Filed: June 17, 2024
    Publication date: October 10, 2024
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Publication number: 20240266200
    Abstract: An electrostatic chuck assembly including a body including a body recess and a heat transfer plate disposed in the body recess, wherein the heat transfer plate includes an upper surface, a lower surface, a first opening, and a second opening. The electrostatic chuck assembly further includes an RF transmission tube configured to transfer RF power to the lower surface of the heat transfer plate. The electrostatic chuck assembly further includes a puck bonded to the upper surface of the heat transfer plate. The electrostatic chuck assembly further includes a first chucking electrode disposed in the first opening and a second chucking electrode is disposed in the second opening, wherein the first and second chucking electrodes are configured to transfer a chucking voltage to the puck.
    Type: Application
    Filed: February 8, 2023
    Publication date: August 8, 2024
    Inventors: Sarath BABU, Mukund SUNDARARAJAN, Cheng-Hsiung TSAI, Ananthkrishna JUPUDI, Ross MARSHALL
  • Patent number: 12046551
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Publication number: 20240242947
    Abstract: Embodiments of a process kit are provided herein. In some embodiments, a deposition ring includes: an annular band having an upper surface and a lower surface, wherein the annular band includes a radially inner portion and a radially outer portion, wherein the lower surface includes a step that extends downward from the radially inner portion to the radially outer portion, wherein the step is disposed closer to a radially outermost surface of the annular band than a radially innermost surface of the annular band; an inner lip extending upwards from the upper surface of the annular band, and wherein the upper surface of the inner lip is an uppermost surface of the deposition ring; a channel disposed radially outward of and beneath a lowermost surface of the annular band; and an outer lip extending upwardly and disposed radially outward of the channel.
    Type: Application
    Filed: March 28, 2024
    Publication date: July 18, 2024
    Inventors: David GUNTHER, Cheng-Hsiung TSAI, Kirankumar Neelasandra SAVANDAIAH
  • Patent number: 11961723
    Abstract: Embodiments of a process kit are provided herein. In some embodiments, a process kit includes a deposition ring configured to be disposed on a substrate support, the deposition ring including an annular band configured to rest on a lower ledge of the substrate support, the annular band having an upper surface and a lower surface, the lower surface including a step between a radially inner portion and a radially outer portion; an inner lip extending upwards from the upper surface of the annular band and adjacent an inner surface of the annular band, wherein a depth between an upper surface of the annular band and a horizontal portion of the upper surface of the inner lip is between about 6.0 mm and about 12.0 mm; a channel disposed radially outward of and beneath the annular band; and an outer lip extending upwardly and disposed radially outward of the channel.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: April 16, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: David Gunther, Cheng-Hsiung Tsai, Kirankumar Neelasandra Savandaiah
  • Patent number: 11955362
    Abstract: Embodiments of substrate supports and process chambers equipped with the same are provided. In some embodiments, a substrate support includes: a support body having a first surface; one or more receptacles extending through the first surface and into the support body; and one or more protrusions respectively disposed within corresponding ones of the one or more receptacles and projecting from the first surface, wherein the one or more protrusions at least partially define a substantially planar support surface above the first surface. Methods of eliminating backside wafer damage are also disclosed.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: April 9, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Joel M Huston, Cheng-Hsiung Tsai, Gwo-Chuan Tzu
  • Publication number: 20240021472
    Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.
    Type: Application
    Filed: May 28, 2023
    Publication date: January 18, 2024
    Inventors: Hwei-Jay CHU, Chieh-Han WU, Hsin-Chieh YAO, Cheng-Hsiung TSAI, Chung-Ju LEE
  • Patent number: 11854820
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee, Jyu-Horng Shieh, Ken-Hsien Hsieh, Ming-Feng Shieh, Shau-Lin Shue, Shih-Ming Chang, Tien-I Bao, Tsai-Sheng Gau
  • Patent number: 11848608
    Abstract: A control circuit for controlling a switching regulator includes a timer, a comparator, a driver circuit and a controller. The timer generates an input signal indicative of whether a predetermined amount of time has elapsed since an activation of a drive signal. The comparator is configured to compare a feedback voltage with a reference voltage to generate a comparison signal. The driver circuit is controlled by a control signal to generate the drive signal according to one of the input signal and the comparison signal. The control signal indicates whether a mode is enabled. When the mode is enabled, the driver circuit is configured to generate the drive signal according to the input signal. The controller is configured to, in response to an activation of the input signal, generate the control signal according to a result of a comparison of the feedback voltage with another reference voltage higher than the reference voltage.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: December 19, 2023
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Chi-Kuang Chang, Cheng-Hsiung Tsai
  • Patent number: 11830910
    Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Han Wu, Hwei-Jay Chu, An-Dih Yu, Tzu-Hui Wei, Cheng-Hsiung Tsai, Chung-Ju Lee, Shin-Yi Yang, Ming-Han Lee
  • Publication number: 20230378255
    Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.
    Type: Application
    Filed: August 2, 2023
    Publication date: November 23, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Han WU, Hwei-Jay CHU, An-Dih YU, Tzu-Hui WEI, Cheng-Hsiung TSAI, Chung-Ju LEE, Shin-Yi YANG, Ming-Han LEE
  • Patent number: 11772137
    Abstract: Methods of cleaning a substrate support comprise: introducing a cleaning gas into a processing chamber containing the substrate support; applying a radio frequency (RF) power to a remote plasma source that is in fluid communication with the processing chamber to establish a reactive etching plasma from the cleaning gas in the processing chamber; reacting deposits on the substrate support with the reactive etching plasma to form a by-products phase; and evacuating the by-products phase from the processing chamber.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: October 3, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Xi Chen, Shreesha Yogish Rao, Sheng Guo, Chi H. Ching, Thomas Blasius Brezoczky, Cheng-Hsiung Tsai
  • Publication number: 20230308018
    Abstract: A control circuit for controlling a switching regulator includes a timer, a comparator, a driver circuit and a controller. The timer generates an input signal indicative of whether a predetermined amount of time has elapsed since an activation of a drive signal. The comparator is configured to compare a feedback voltage with a reference voltage to generate a comparison signal. The driver circuit is controlled by a control signal to generate the drive signal according to one of the input signal and the comparison signal. The control signal indicates whether a mode is enabled. When the mode is enabled, the driver circuit is configured to generate the drive signal according to the input signal. The controller is configured to, in response to an activation of the input signal, generate the control signal according to a result of a comparison of the feedback voltage with another reference voltage higher than the reference voltage.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Chi-Kuang Chang, Cheng-Hsiung Tsai
  • Publication number: 20230265561
    Abstract: A substrate support includes a monolithic body. The monolithic body includes a central portion and a peripheral portion. The central portion includes a top surface recessed with respect to the peripheral portion. A shadow ring is configured to sit directly upon an upper surface of the peripheral portion, and overlaps a portion of a substrate positioned upon the central portion. A heating element embedded within the central portion heats the central portion, the peripheral portion, and the shadow ring.
    Type: Application
    Filed: May 23, 2022
    Publication date: August 24, 2023
    Inventors: Zubin HUANG, Tomoharu MATSUSHITA, Cheng-Hsiung TSAI
  • Publication number: 20230253312
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 11676862
    Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hwei-Jay Chu, Chieh-Han Wu, Hsin-Chieh Yao, Cheng-Hsiung Tsai, Chung-Ju Lee
  • Patent number: D1040304
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: August 27, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: David Gunther, Cheng-Hsiung Tsai, Kirankumar Neelasandra Savandaiah