Abstract: The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.

Abstract: A heat dissipating semiconductor package and a heat dissipating structure thereof are provided. The heat dissipating structure includes an outer surface, consecutive recessed step portions, and a pressure-releasing groove. The outer surface is exposed from an encapsulant made of a molding compound. The step portions are formed at an edge of the outer surface and have decreasing depths wherein the closer a step portion to a central position of the outer surface, the smaller the depth of this step portion is. The pressure-releasing groove is disposed next to and deeper than the innermost one of the step portions. A molding compound flows to the step portions and absorbs heat from an encapsulation mold quickly, such that a flowing speed of the molding compound is reduced. Pressure suffered by air remaining at the step portions is released through the pressure-releasing groove, thereby preventing flashes of the molding compound and resin bleeding.

Abstract: The present invention provides a semiconductor package and a fabrication method thereof. The method includes the steps of: providing a chip carrier module having a plurality of chip carriers, disposing a plurality of electrical connecting points on the chip carriers, performing chip mounting and molding on the chip carrier module to form an encapsulant encapsulating the semiconductor chip, exposing the electrical connecting points from the encapsulant; forming a patterned circuit layer on the encapsulant, electrically connecting the patterned circuit layer to the electrical connecting points, cutting and separating the chip carriers to form a plurality of semiconductor packages each having a circuit layer formed on the encapsulant such that the circuit layer provides extra electrical connecting points and thereby enhances electrical performance of electrical products. During a package stacking process, no package is limited by the design of another package below.

Abstract: A semiconductor package and a method for fabricating the same are disclosed. The method includes installing a plurality of conductive components on a plurality of chip carriers of a chip carrier module, connecting electrically the conductive components to electrical connection points of the adjacent chip carriers, mounting and electrically connecting a semiconductor chip to each of the chip carries, forming an encapsulant for enveloping the semiconductor chip and the conductive components, cutting the chip carriers to separate the conductive components installed thereon, exposing a portion of the conductive components out of the encapsulant, forming on the exposed portion of the conductive components an electroplated layer of nickel/gold, and separating the chip carriers from each other. The conductive components exposed out of the encapsulant provide extra electrical connection points and thereby promote the functionalities of electronic products.

Abstract: A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

Abstract: A semiconductor device, a chip structure thereof, and a method for fabricating the same are proposed. The method involves cutting a wafer with an array of chips twice so as to separate the chips and to form a chip structure. The first cutting is wider than the second cutting, and both are performed on an inactive surface of each of the chips. The chip structure includes a protruding portion formed on the inactive surface. The chip structure is electrically connected to a substrate by conductive bumps in a flip-chip manner and mounted with a heat sink. A decrease in contact area between the chip and the heat sink reduces warpage caused to the semiconductor device by thermal stress, thus preventing delamination of the heat sink and cracking of the conductive bumps, and reducing the expense and time spent on finding suitable underfill materials.

Abstract: A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.

Abstract: A semiconductor package with a heat sink and a method for fabricating the same are proposed. A first adhesive of a low Young's modulus is disposed on a corner region of a heat sink mounting area of a substrate. A second adhesive of a high Young's modulus is disposed on the heat sink mounting area except the corner region. The heat sink is mounted on the heat sink mounting area and thereby secured in position to the substrate, by the first and second adhesives. The disposition of the first and second adhesives of different Young's moduli not only prevents detachment of the heat sink from the substrate, but also controls the flatness of the heat sink. The prevent invention does not affect the appearance of the semiconductor package and its ensuing assembly process.

Abstract: A bump structure of a semiconductor package and a method for fabricating the same are provided. The bump structure is used to connect a semiconductor element to a carrier of the semiconductor package. The fabrication method primarily employs an electroplating process to form the bump structure including an under bump metallurgy (UBM) layer, at least one I-shaped conductive pillar, and a solder material. This allows fine-pitch electrical connection pads to be arranged in the semiconductor package, and also provides an enhanced support structure and a sufficient height between the semiconductor element and the carrier.

Abstract: A semiconductor package with a heat dissipating device and a fabrication method of the semiconductor package are provided. A chip is mounted on a substrate. The heat dissipating device is mounted on the chip, and includes an accommodating room, and a first opening and a second opening that communicate with the accommodating room. An encapsulant is formed between the heat dissipating device and the substrate to encapsulate the chip. A cutting process is performed to remove a non-electrical part of structure and expose the first and second openings from the encapsulant. A cooling fluid is received in the accommodating room to absorb and dissipate heat produced by the chip. The heat dissipating device covers the encapsulant and the chip to provide a maximum heat transfer area for the semiconductor package.

Abstract: A semiconductor package and a method for fabricating the same are provided. The method includes providing a substrate having recognition points and a heat sink having openings, and placing the heat sink on the substrate with the recognition points being exposed through the openings; using a checking system to inspect the recognition points through the openings so as to ensure that the heat sink is placed at a predetermined position on the substrate; and attaching the heat sink to the substrate via an adhesive. By the above semiconductor package and method, there is no need to form positioning holes in the substrate such that any adverse effect on the circuit layout and reliability of the semiconductor package is avoided, and any positional shifting of the heat sink relative to the substrate can be determined in a real time manner.

Abstract: A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.

Abstract: A flip-chip semiconductor device and a method for fabricating the same are provided. A first underfill material with a low Young's modulus is applied to corners of a chip mounting area defined on a substrate. A chip is mounted on and electrically connected to the chip mounting area by a plurality of conductive bumps, allowing the first underfill material to encapsulate corners of the chip. A second underfill material with a high Young's modulus is used to fill a gap between the chip and the substrate to protect the conductive bumps and support the chip.

Abstract: A semiconductor device and the fabrication method thereof are provided.

Abstract: A method for fabricating semiconductor packages includes the steps of: providing a plurality of substrates and a carrier having a plurality of openings, wherein, each of the substrates has at least one chip (die) disposed thereon, length and width of the substrates are approximately equal to the predefined length and width of semiconductor packages, and length and width of the openings of the carrier are bigger than length and width of the substrates; respectively positioning the substrates in the openings of the carrier and blocking the gaps between the substrates and the carrier so as to prevent the gaps from penetrating through the carrier; performing a mold press process so as to form an encapsulant on each of the openings for encapsulating the chip, wherein length and width of the area covered by the encapsulant are bigger than length and width of the opening; performing a mold releasing process; and cutting along edges of the substrates according to the predefined length and width of semiconductor packa

Abstract: An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. An opening is formed in the protective layer to expose at least three sides of each of the paired bond pads. The protective layer includes at least one independent residual portion located in the opening and between the paired bond pads, such that an electronic component is mounted on the independent residual portion and electrically connected to the bond pads. A groove without a dead space is formed between the electronic component and the carrier, such that a molding compound for encapsulating the electronic component can flow through the groove to fill the opening and a space under the electronic component and encapsulate the at least three sides of each of the bond pads.

Abstract: A semiconductor package and a substrate structure thereof are provided. A solder mask layer applied on the substrate structure is formed with outwardly extended openings corresponding to corner portions of a chip mounting area of the substrate structure. When a flip-chip semiconductor chip is mounted on the chip mounting area and an underfilling process is performed, an underfill material can fill a gap between the flip-chip semiconductor chip and the substrate structure, and effectively fill the outwardly extended openings of the solder mask layer corresponding to the corner portions of the chip mounting area so as to provide sufficient protection for corners of the flip-chip semiconductor chip and prevent delamination at the corners of the flip-chip semiconductor chip during a subsequent thermal cycle.

Abstract: A semiconductor package and a method for fabricating the same are proposed. A substrate having a first circuit layer, a second circuit layer, and a core layer formed between the first and second circuit layers is provided. At least one second opening is formed on the second circuit layer. At least one first opening is formed on the first circuit layer corresponding to the second opening. A plurality of finger holes corresponding to bond fingers on the first circuit layer are formed in the core layer. A through opening is formed in the core layer and communicates with the first and second openings. At least one chip is mounted on the first circuit layer and covers the first opening, with its active surface being exposed to the first opening. An encapsulant is formed to fill the first and second openings and the through opening and encapsulate the chip.

Abstract: A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a plurality of grooves or holes at positions in contact with the substrate, allowing an adhesive material to be applied between the heat sink and the substrate and filled into the grooves or holes for attaching the heat sink onto the substrate. The adhesive material filled into the grooves or holes provides an anchoring effect for firmly positioning the heat sink on the substrate. Therefore, it is not necessary to form predetermined holes on the substrate for being coupled to fixing members such as bolts, and incorporation of the heat sink would not affect trace routability and arrangement of input/output connections such as solder balls on the substrate and would not lead to cracks of the chip.

Abstract: A method is provided of making a semiconductor package with a heat spreader in which a chip carrier module plate consisting of a plurality of array-arranged chip carriers is mounted with at least one chip on each of the chip carriers. A heat spreader module plate is attached to the chips, with an interface layer formed on a top surface of the heat spreader module plate. The chip carrier module plate, the chips and the heat spreader module plate are encapsulated. Adhesion force between the interface layer and the encapsulant is larger than that between the interface layer and the heat spreader module plate, and adhesion force between the interface layer and the heat spreader module plate is smaller than that between the heat spreader module plate and the encapsulant.