Abstract: A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.

Abstract: A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a plurality of grooves or holes at positions in contact with the substrate, allowing an adhesive material to be applied between the heat sink and the substrate and filled into the grooves or holes for attaching the heat sink onto the substrate. The adhesive material filled into the grooves or holes provides an anchoring effect for firmly positioning the heat sink on the substrate. Therefore, it is not necessary to form predetermined holes on the substrate for being coupled to fixing members such as bolts, and incorporation of the heat sink would not affect trace routability and arrangement of input/output connections such as solder balls on the substrate and would not lead to cracks of the chip.

Abstract: A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.

Abstract: A heat-dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted and electrically connected to a substrate. A heat-dissipating structure includes a heat sink and at least one supporting portion, wherein the supporting portion is attached to the substrate at a position outside a predetermined package area for the semiconductor package, and the semiconductor chip is disposed under the heat sink. An encapsulant is formed on the substrate to encapsulate the semiconductor chip and the heat-dissipating structure, wherein a projection area of the encapsulant on the substrate is larger in size than the predetermined package area. A cutting process is performed along edges of the predetermined package area to remove parts of the encapsulant, the supporting portion and the substrate, which are located outside the predetermined package area, so as to form the semiconductor package integrated with the heat-dissipating structure.

Abstract: A flip-chip semiconductor device is proposed, including a substrate, a plurality of stiffeners disposed at peripheral areas of the substrate, with a gap formed between each of the adjacent stiffeners; at least a semiconductor chip mounted on an area of the substrate surrounded by the stiffeners via flip-chip technique; and a beat sink attached to the semiconductor chip. By such arrangement, warpage of the semiconductor device may be prevented. As an opening is formed at an appropriate position of the stiffener structure, distortion of the stiffener may be avoided. Further, as the beat sink is not attached to the stiffener, solder bumps may be free from thermal stress due to mismatch in coefficient of thermal expansion between the heat sink and the substrate while preventing delamination of the heat sink caused by thermal stress.

Abstract: A semiconductor package having conductive bumps on a chip and a fabrication method thereof are provided. A plurality of the conductive bumps are deposited respectively on bond pads of the chip. An encapsulation body encapsulates the chip and conductive bumps while exposing ends of the conductive bumps. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the exposed ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings for exposing predetermined portions of the conductive traces. The exposed portions of the conductive traces are connected to a plurality of solder balls respectively. The conductive bumps on the bond pads of the chip allow easy positional recognition of the bond pads, making the conductive traces well electrically connected to the bond pads through the conductive bumps and assuring the quality and reliability of the semiconductor package.

Abstract: A sensor module structure and a method for fabricating the same are proposed. A chip carrier module plate including a plurality of chip carriers is provided, each chip carrier having a first surface and a second surface. At least one semiconductor chip is mounted on and electrically connected to the first surface of each of the chip carriers. An encapsulation body is formed for completely encapsulating the semiconductor chips and the first surfaces of the chip carriers. A singulation process is performed to form individual package units integrated with the semiconductor chips. A sensor chip, a corresponding lens kit and a flexible printed circuit (FPC) board are attached to the second surface of each of the chip carriers, wherein the sensor chip and the FPC board are electrically connected to the chip carrier. This provides the sensor module structure fabricated with simple processes, low costs and high yields.

Abstract: A flip-chip semiconductor package and a method for fabricating the same are proposed. A flux is formed on surfaces of solder bumps mounted on an active surface of a semiconductor chip, wherein the acid number of the flux is greater than 20 and the viscosity of the flux is greater than 40. When the chip is electrically connected to a lead frame via the solder bumps by a reflowing process, the flux allows the chip to be effectively fixed to the lead frame and makes the solder bumps not easily wetted to the lead frame during the reflowing process, so as to prevent over-collapsing of the solder bumps.

Abstract: A semiconductor element with under bump metallurgy (UBM) structures and a fabrication method thereof are proposed. When UBM structures are formed on signal pads and ground pads on a surface of the semiconductor element that is completely fabricated with a circuit layout, a metallic layer for defining the UBM structures is retained, wherein the UBM structures on the ground pads are electrically connected to the metallic layer, and the UBM structures on the signal pads are electrically insulated from the metallic layer. This allows the metallic layer for defining the UBM structures to directly serve as a grounding layer for the semiconductor element.

Abstract: A semiconductor package with a heat sink is proposed, in which a chip has its first surface attached to a chip carrier, while a second surface of the chip is attached to a heat sink through an adhesive, allowing heat generated by the chip to be transmitted to the heat sink. Moreover, in a molding process, a molding resin is used to form an encapsulant for encapsulating the chip, while a top surface and side surfaces connected to the top surface of the heat sink are exposed to outside of the encapsulant, that is, the heat sink merely has its bottom surface bonded to the encapsulant. This makes the generated heat directly dissipated to the atmosphere through the heat sink. Furthermore, the top surface of the heat sink is coated with an interface layer, while adhesion between the interface layer and the molding resin is smaller than that between the heat sink and the encapsulant.

Abstract: A semiconductor package and a fabrication method of the same are proposed. A chip formed with a plurality of electrode pads on an active surface thereof, and a substrate having a first surface, a corresponding second surface and at least one opening penetrating therethrough are provided. A part of the electrode pads of the chip are electrically connected to the second surface of the substrate by bonding wires passing through the opening of the substrate, and the rest of the electrode pads of the chip are electrically connected to the first surface of the substrate by conductive bumps. A molding process is performed to form a first encapsulant on the first surface of the substrate for encapsulating the chip and form a second encapsulant on the second surface of the substrate for encapsulating the bonding wires. A plurality of solder balls are implanted on the second surface of the substrate.

Abstract: A process applied to grinding, dicing, and/or stacking semiconductors is disclosed. One feature of the process is that after transparent material is stuck on its active surface, a semiconductor is ground from another surface thereof to become thinner, then the semiconductor is diced, by taking advantage of transparency of the transparent material, from its active surface, to obtain at least one smaller semiconductor unit such as die/dice or chip(s). Another feature is that the transparent material remains sticking to the active surface of the die by an adhesion layer until the die is attached to a carrier or another die, and then the transparent material and the adhesion layer are removed by taking advantage of a function of the adhesion layer: receiving a ray to lose adhesion between it and the active surface. Preferably the ray reaches the adhesion layer via the transparent material stuck on the active surface of the die.

Abstract: A thermally enhanced semiconductor package and a fabrication method thereof are provided. A plurality of conductive bumps are formed on bond pads on an active surface of a chip. A heat sink is attached to an inactive surface of the chip and has a surface area larger than that of the chip. An encapsulation body encapsulates the heat sink, chip and conductive bumps, while exposing a bottom or surfaces, not for attaching the chip, of the heat sink and ends of the conductive bumps outside. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with a plurality of openings for exposing predetermined portions of the conductive traces. A solder ball is implanted on each exposed portion of the conductive traces.

Abstract: A semiconductor package having conductive bumps on a chip and a fabrication method thereof are provided. A plurality of the conductive bumps are deposited respectively on bond pads of the chip. An encapsulation body encapsulates the chip and conductive bumps while exposing ends of the conductive bumps. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the exposed ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings for exposing predetermined portions of the conductive traces. The exposed portions of the conductive traces are connected to a plurality of solder balls respectively. The conductive bumps on the bond pads of the chip allow easy positional recognition of the bond pads, making the conductive traces well electrically connected to the bond pads through the conductive bumps and assuring the quality and reliability of the semiconductor package.

Abstract: A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; an encapsulant formed on the chip carrier and for encapsulating the chip, with a non-active surface of the chip being exposed from the encapsulant; and a heat spreader having a hollow portion and attached to the encapsulant, wherein the chip is received in the hollow portion and the non-active surface of the chip is completely exposed to the hollow portion, such that heat generated by the chip can be directly dissipated out of the package structure. The present invention also provides a method for fabricating the heat dissipating package structure.

Abstract: A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; a heat spreader having a first surface, an opposed second surface and a hollow structure, the second surface of the heat spreader being mounted on the chip, wherein the chip is larger in size than the hollow structure such that the chip is partly exposed to the hollow structure; an encapsulant formed between the heat spreader and the chip carrier, for encapsulating the chip, wherein the first surface and sides of the heat spreader are exposed from the encapsulant to dissipate heat produced from the chip; and a plurality of conductive elements disposed on the chip carrier, for electrically connecting the chip to an external device. The present invention also provides a method for fabricating the heat dissipating package structure.

Abstract: A thermally enhanced semiconductor package and a fabrication method thereof are provided. A plurality of conductive bumps are formed on bond pads on an active surface of a chip. A heat sink is attached to an inactive surface of the chip and has a surface area larger than that of the chip. An encapsulation body encapsulates the heat sink, chip and conductive bumps, while exposing a bottom or surfaces, not for attaching the chip, of the heat sink and ends of the conductive bumps outside. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with a plurality of openings for exposing predetermined portions of the conductive traces. A solder ball is implanted on each exposed portion of the conductive traces.

Abstract: A bump structure of a semiconductor package and a method for fabricating the same are provided. The bump structure is used to connect a semiconductor element to a carrier of the semiconductor package. The fabrication method primarily employs an electroplating process to form the bump structure including an under bump metallurgy (UBM) layer, at least one I-shaped conductive pillar, and a solder material. This allows fine-pitch electrical connection pads to be arranged in the semiconductor package, and also provides an enhanced support structure and a sufficient height between the semiconductor element and the carrier.

Abstract: A semiconductor package with a photosensitive chip and a fabrication method thereof are provided. A substrate having a core is prepared. A solder mask layer is applied over a surface of the core and formed with an opening to expose a continuous peripheral portion on the surface of the core. At least one photosensitive chip is mounted on and electrically connected to the substrate. An encapsulation dam is formed on the continuous peripheral portion of the core and surrounds the chip. The dam includes a shoulder portion adjacent to and flush with the solder mask layer, and a protruded support portion surrounding the shoulder portion. A lid is attached to the support portion of the dam for sealing the dam such that the chip is received in a space defined by the substrate, the dam and the lid.