Patents by Inventor Cheng-Hung Chang

Cheng-Hung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200225551
    Abstract: A reflective display device includes a thin-film transistor (TFT) array substrate, a front panel laminate (FPL), a front protection sheet, a back protection sheet, a light blocking layer, and a light source. The front panel laminate is located on the TFT array substrate, and has a transparent conductive layer and a display medium layer. The display medium layer is located between the transparent conductive layer and the TFT array substrate. The front protection sheet is located on the front panel laminate. The back protection sheet is located below the TFT array substrate. The light blocking layer at least covers a lateral surface of the back protection sheet. The light source faces toward a lateral surface of the front panel laminate, a lateral surface of the TFT array substrate, and the lateral surface of the back protection sheet.
    Type: Application
    Filed: July 24, 2019
    Publication date: July 16, 2020
    Inventors: Chia-Chi CHANG, Chih-Chun CHEN, Chi-Ming WU, Yi-Ching WANG, Jia-Hung CHEN, Cheng-Hsien LIN
  • Publication number: 20200184611
    Abstract: A depth decoding system and a method for rectifying a ground-truth image are introduced. The depth decoder system includes a projector, a camera, a processor and a decoder. The projector is configured to project a structural light pattern to a first reference plane and a second reference plane. The camera is configured to capture a first ground-truth image from the first reference plane and capture a second ground-truth image from the second reference plane. The processor is configured to perform a rectification operation to the first ground-truth image and the second ground-truth image to generate a rectified ground-truth image. The decoder is configured to generate a depth result according to the rectified ground-truth image.
    Type: Application
    Filed: July 7, 2019
    Publication date: June 11, 2020
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Chin-Jung Tsai, Yu-Hsuan Chu, Cheng-Hung Chi, Ming-Shu Hsiao, Nai-Ting Chang, Yi-Nung Liu
  • Patent number: 10673813
    Abstract: The present invention provides a method for NAT traversal in VPN so that the VPN can detect the rule of port allocation for NAT outside the VPN to achieve NAT traversal. The communication structure according to the present invention includes a public network, a client network, a destination network, a first NAT, a second NAT. A DNAT-T proxy server is installed between the first NAT and the second NAT and has the function for the VPN to conduct a plurality of (N times) registrations before sending data out to detect the rule for NAT port allocation of the DNAT-T proxy server, and then inform the next NAT port allocation to the other side of the VPN so as to achieve NAT traversal for the data packets in VPN.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 2, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Hsueh Ming Hang, Shaw Hwa Hwang, Cheng Yu Yeh, Bing Chih Yao, Kuan Lin Chen, Yao Hsing Chung, Shun Chieh Chang, Chi Jung Huang, Li Te Shen, Ning Yun Ku, Tzu Hung Lin, Ming Che Yeh
  • Publication number: 20200169537
    Abstract: A system including a network communication device, a storage device, and a controller is provided. The storage device stores first mappings between IP addresses and devices, and second mappings between software and devices. The controller obtains a connection log from the proxy server or the firewall device via the network communication device, uses the first mappings and the second mappings to analyze the connection log to determine one or more different connections between connections of devices on which first software is installed and connections of devices on which the first software is not installed, determines whether the first software functions normally on a first device blocking the different connections, and adds destination addresses of the different connections into a blocking list in response to the first software functioning normally on the first device, such that the proxy server or the firewall device blocks all connections towards the destination addresses.
    Type: Application
    Filed: March 19, 2019
    Publication date: May 28, 2020
    Inventors: Chen-Chung LEE, Chia-Hung LIN, Cheng-Yao WANG, Jen-Hung CHANG, Ming-Jen CHEN
  • Patent number: 10665550
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu Lee, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng, Ka Fai Chang
  • Patent number: 10658799
    Abstract: A transmission cable including a signal wire and a shielding layer is provided. The signal wire is configured to transmit a differential signal provided by an eDP interface or a V-by-one interface. The shielding layer is configured to cover the signal wire. An end of the signal wire receives the differential signal provided by the eDP interface or the V-by-one interface, and another end of the signal wire outputs the differential signal provided by the eDP interface or the V-by-one interface. In addition, a display system is also provided.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: May 19, 2020
    Assignee: Innolux Corporation
    Inventors: Chih-Yang Hsu, Chien-Hung Chen, Heng-Chang Chang, Chin-Lung Ting, Cheng-Te Wang
  • Patent number: 10637259
    Abstract: A short-circuit current protecting method of a charging control system is cooperating with at least a control unit and a plurality of power outlet electrically connected to an electronic switch. The control unit controls the mode of the electronic switches with turn on or off. The short-circuit current protecting method includes the following steps. Step 1 is detecting at least a current signal value of an AC power. Step 2 is determining whether the current signal value is grater than a predetermine current threshold. Step 3 is enabling a short-circuit current analyzing module if the current signal value is grater than the predetermine current threshold. Step 4 is turning off at least one of the electronic switches if the short-circuit current is determined by the short-circuit current analyzing module.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: April 28, 2020
    Assignee: AVER INFORMATION INC.
    Inventors: Chi-Fa Hsu, Chao-Hung Chang, Lien-Kai Chou, Cheng-Cheng Yu
  • Publication number: 20200126976
    Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Yu CHEN, Chih-Ping CHAO, Chun-Hung CHEN, Chung-Long CHANG, Kuan-Chi TSAI, Wei-Kung TSAI, Hsiang-Chi CHEN, Ching-Chung HSU, Cheng-Chang HSU, Yi-Sin WANG
  • Publication number: 20200116342
    Abstract: A lamp, a lamp system, a method for assembling a lamp system, and a method for disassembling a lamp system are provided. The lamp includes a frame body, a light guide plate, a light source, and a connecting mechanism. The frame body includes two side covers and two end caps. An accommodating space is formed among the side covers and the end caps. The light guide plate is disposed in the accommodating space. The light source is disposed in one of the side covers. The connecting mechanism includes an electrical connecting assembly and a suspension member. The electrical connecting assembly is connected to the light source to form an electrical loop. Each of the end caps has a groove, and one end of the suspension member is passed through one of the grooves from a first end of the groove and is positioned in a second end of the groove.
    Type: Application
    Filed: October 9, 2019
    Publication date: April 16, 2020
    Inventors: Chih-Hung JU, Cheng-Ang CHANG, Shang-Chia LIU
  • Publication number: 20200111887
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 9, 2020
    Inventors: DE-FANG CHEN, TENG-CHUN TSAI, CHENG-TUNG LIN, LI-TING WANG, CHUN-HUNG LEE, MING-CHING CHANG, HUAN-JUST LIN
  • Patent number: 10613583
    Abstract: A system includes a chassis assembly, a first boss component secured to the chassis assembly, and a second boss component secured to the chassis assembly. A first tab-bracket is secured to the first boss component and a second tab bracket is secured to the second boss component. Each tab-bracket includes a portion having adhesive applied thereon. A battery is affixed to the adhesive at the first tab-bracket and to the adhesive at the second tab-bracket after the tab-brackets are secured to the boss components.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 7, 2020
    Assignee: Dell Products, L.P.
    Inventors: Yao-Tsung Chang, Chia-Min Sun, Cheng-Hung Chen
  • Publication number: 20200043873
    Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.
    Type: Application
    Filed: June 12, 2019
    Publication date: February 6, 2020
    Inventors: Fong-yuan CHANG, Cheng-Hung YEH, Hsiang-Ho CHANG, Po-Hsiang HUANG, Chin-Her CHIEN, Sheng-Hsiung CHEN, Aftab Alam KHAN, Keh-Jeng CHANG, Chin-Chou LIU, Yi-Kan CHENG
  • Publication number: 20200019668
    Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.
    Type: Application
    Filed: July 2, 2019
    Publication date: January 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan CHANG, Chin-Chou Liu, Chin-Her CHIEN, Cheng-Hung YEH, Po-Hsiang HUANG, Sen-Bor Jan, Yi-Kan Cheng, Hsiu-Chuan Shu
  • Publication number: 20200020644
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu LEE, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng, Ka Fai Chang
  • Patent number: 10515949
    Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Yu Chen, Chih-Ping Chao, Chun-Hung Chen, Chung-Long Chang, Kuan-Chi Tsai, Wei-Kung Tsai, Hsiang-Chi Chen, Ching-Chung Hsu, Cheng-Chang Hsu, Yi-Sin Wang
  • Patent number: 10510830
    Abstract: An N-type polysilicon crystal, a manufacturing method thereof, and an N-type polysilicon wafer are provided. The N-type polysilicon crystal has a slope of resistivity and a slope of defect area percentage. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to resistivity presented by a unit of Ohm·cm (?·cm), the slope of resistivity is 0 to ?1.8 at the solidified fraction of 0.25 to 0.8. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to defect area percentage (%), the slope of defect area percentage is less than 2.5 at the solidified fraction of 0.4 to 0.8.
    Type: Grant
    Filed: September 2, 2018
    Date of Patent: December 17, 2019
    Assignee: Sino-American Silicon Products Inc.
    Inventors: Ching-Hung Weng, Cheng-Jui Yang, Yu-Min Yang, Yuan-Hsiao Chang, Bo-Kai Wang, Wen-Huai Yu, Ying-Ru Shih, Sung-Lin Hsu
  • Patent number: 10505014
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
  • Publication number: 20190371323
    Abstract: A voice control device includes a user database, a first image capturing module, a voice command module and a management module. The user database stores first user identification data of a first user account. The first image capturing module captures an environmental image. The voice command module is enabled to receive a voice command for controlling the voice control device. The management module is used to detect whether at least one facial image exists in the environmental image, and detect whether the facial image matches with the first user identification data, and when the facial image matches with the first user identification data, the management module logs in the first user account and enables the voice command module.
    Type: Application
    Filed: April 15, 2019
    Publication date: December 5, 2019
    Inventors: CHENG-YU KAO, NIEN-CHIH WANG, YU-HUNG TSENG, YUEH-FEI CHANG, CHIH-LUN WANG
  • Patent number: 10498147
    Abstract: A power charging management method is cooperated with a charging control system. The charging control system includes a control unit and a plurality of charging zones. The control unit controls the charging zones to turn on or turn off so as to selectively allow a charging power to be provided to the charging zones. The power charging management method includes a system scan procedure, a whole zone charging procedure, a protecting procedure and a subzone charging procedure.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: December 3, 2019
    Assignee: AVER INFORMATION INC.
    Inventors: Chi-Fa Hsu, Chao-Hung Chang, Lien-Kai Chou, Cheng-Cheng Yu, Jy-Shyan Lin
  • Publication number: 20190331975
    Abstract: A display panel including a pixel array substrate, an opposite substrate, and a display media is provided. The pixel array substrate includes a substrate, a plurality of scan lines, a plurality of data lines, a plurality of pixel units, and a gate driving circuit. The gate driving circuit including a plurality of first signal lines, a plurality of second signal lines, a plurality of dummy signal lines, and a plurality of contact structures is disposed in a peripheral region of the substrate. Each of the second signal lines is electrically connected to one corresponding first signal line. Each of the dummy signal lines is electrically connected to one corresponding second signal line via one corresponding contact structure. Each of the first signal lines is electrically connected to the corresponding second signal line via one corresponding contact structure.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 31, 2019
    Applicant: Au Optronics Corporation
    Inventors: Cheng-Hung Ko, Yi-Fu Chen, Yu-Sen Chang, Chia-Heng Chen, Hsiao-Chun Chen, You-Ying Lin, Cheng-An Hsieh