Patents by Inventor Cheng-Hung Chang
Cheng-Hung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11959623Abstract: The present disclosure provides a connecting device and a lamp system. The connecting device is used to connect multiple lamps to form the lamp system. The connecting device includes a connecting element, a cover, and a shell. The cover is mounted on the connecting element and includes at least two first assembling members. The shell is detachably mounted on the cover. The shell includes a side wall, an opening, multiple gateways, and at least two second assembling members. The side wall surrounds a space. The opening and the gateways all are formed on a top of the side wall and communicate with the space. A portion of each of the lamps is received in one of the gateways. The second assembling members are disposed on the side wall and face each other in a radial line of the shell, and respectively engage with the first assembling members.Type: GrantFiled: April 27, 2023Date of Patent: April 16, 2024Assignee: Radiant Opto-Electronics CorporationInventors: Chih-Hung Ju, Cheng-Ang Chang, Guo-Hao Huang, Chung-Kuang Chen
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Publication number: 20240096998Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.Type: ApplicationFiled: November 21, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin LIANG, Chij-chien CHI, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG, Cheng-Wei CHANG, Chein-Shun LIAO, Keng-chu LIN, KAi-Ting HUANG
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Publication number: 20240068652Abstract: The present disclosure provides a connecting device and a lamp system. The connecting device is used to connect multiple lamps to form the lamp system. The connecting device includes a connecting element, a cover, and a shell. The cover is mounted on the connecting element and includes at least two first assembling members. The shell is detachably mounted on the cover. The shell includes a side wall, an opening, multiple gateways, and at least two second assembling members. The side wall surrounds a space. The opening and the gateways all are formed on a top of the side wall and communicate with the space. A portion of each of the lamps is received in one of the gateways. The second assembling members are disposed on the side wall and face each other in a radial line of the shell, and respectively engage with the first assembling members.Type: ApplicationFiled: April 27, 2023Publication date: February 29, 2024Inventors: Chih-Hung JU, Cheng-Ang CHANG, Guo-Hao HUANG, Chung-Kuang CHEN
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Patent number: 11915746Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.Type: GrantFiled: May 12, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-jer Hsieh, Yu-Hao Hsu, Zhi-Hao Chang, Cheng Hung Lee
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Patent number: 11916131Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: GrantFiled: November 4, 2020Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
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Publication number: 20240005120Abstract: The present invention provides an RFID yarn module comprising a polymer substrate having a first surface and a second surface opposite to the first surface, a metal layer, and a first adhesive layer formed on the metal layer, and a first polymer material layer formed on the first the adhesive layer, a second adhesive layer, and a first protection layer. The metal layer is formed on the first surface of the polymer substrate and has an RFID element electrically connected to the metal layer. The second adhesive layer is formed on the first polymer material layer and is corresponding to the RFID element. The first protection layer is formed on the second adhesive layer. Alternatively, the present invention provides a method for making the RFID yarn module in which a roll-to-roll process for mass manufacturing is utilized to make the RFID yarn module.Type: ApplicationFiled: October 14, 2022Publication date: January 4, 2024Applicant: Securitag Assembly Group Co., Ltd.Inventors: Chong En DAI, Cheng Hung CHANG
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Patent number: 11545392Abstract: A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T1 at a first end of the opening, and a thickness T2 at a second end of the opening, and R1 is a ratio of T1 to T2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T3 at the first end of the opening, a thickness T4 at the second end of the opening, R2 is a ratio of T3 to T4, and R1 is greater than R2.Type: GrantFiled: September 15, 2020Date of Patent: January 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 11133387Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.Type: GrantFiled: June 3, 2019Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Chen-Hua Yu, Chen-Nan Yeh
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Patent number: 11114563Abstract: Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.Type: GrantFiled: April 2, 2018Date of Patent: September 7, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Hua Yu
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Patent number: 11038056Abstract: System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.Type: GrantFiled: February 10, 2012Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. Hsin-Chu, TaiwanInventors: Chen-Hua Yu, Cheng-Hung Chang, Chen-Nan Yeh, Yu-Rung Hsu
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Publication number: 20210005515Abstract: A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T1 at a first end of the opening, and a thickness T2 at a second end of the opening, and R1 is a ratio of T1 to T2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T3 at the first end of the opening, a thickness T4 at the second end of the opening, R2 is a ratio of T3 to T4, and R1 is greater than R2.Type: ApplicationFiled: September 15, 2020Publication date: January 7, 2021Inventors: Chen-Hua YU, Cheng-Hung CHANG, Ebin LIAO, Chia-Lin YU, Hsiang-Yi WANG, Chun Hua CHANG, Li-Hsien HUANG, Darryl KUO, Tsang-Jiuh WU, Wen-Chih CHIOU
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Patent number: 10784162Abstract: A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.Type: GrantFiled: October 23, 2018Date of Patent: September 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20190288070Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.Type: ApplicationFiled: June 3, 2019Publication date: September 19, 2019Inventors: Cheng-Hung Chang, Chen-Hua Yu, Chen-Nan Yeh
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Patent number: 10312327Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.Type: GrantFiled: July 31, 2017Date of Patent: June 4, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Chen-Hua Yu, Chen-Nan Yeh
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Patent number: 10242308Abstract: The present invention provides a radio frequency identification and sensing device comprising an antenna module, a RFID sensing module, and battery module. The antenna module has a first flexible substrate having an antenna circuit formed thereon. The RFID sensing module comprises a second flexible substrate, a RFID chip, a sensor formed on the second flexible substrate and a memory module formed on the second flexible substrate, wherein the sensor is utilized to detecting an environmental status for generating a plurality of sensing data, and the memory module is utilized to store the plurality of sensing data. The RFID chip is utilized to transfer the plurality of data to a reading device. The battery module is utilized to provide electrical power for operating the RFID sensing module.Type: GrantFiled: February 24, 2017Date of Patent: March 26, 2019Assignee: Securitag Assembly Group Co., LtdInventors: Tian lin Yan, Cheng hung Chang, Way Yu Chen
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Publication number: 20190067107Abstract: A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.Type: ApplicationFiled: October 23, 2018Publication date: February 28, 2019Inventors: Chen-Hua YU, Cheng-Hung CHANG, Ebin LIAO, Chia-Lin YU, Hsiang-Yi WANG, Chun Hua CHANG, Li-Hsien HUANG, Darryl KUO, Tsang-Jiuh WU, Wen-Chih CHIOU
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Patent number: 10166707Abstract: The present invention provides an RFID device and manufacturing method. The RFID device comprises a first housing, an antenna module, and a second housing. The antenna module arranged on the first housing comprises a base substrate, and an antenna layer, sticking on an outer surface of the base substrate. The second housing is formed to couple to the first housing by an injection molding process so that the antenna module is arranged between the first and second housings.Type: GrantFiled: December 19, 2017Date of Patent: January 1, 2019Assignee: SECURITAG ASSEMBLY GROUP CO., LTDInventors: Cheng hung Chang, Ching Mei Chi, Chun Jun Chuang, Ya Chi Shen, Tian lin Yan
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Patent number: 10115634Abstract: A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.Type: GrantFiled: July 20, 2016Date of Patent: October 30, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20180226506Abstract: Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.Type: ApplicationFiled: April 2, 2018Publication date: August 9, 2018Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Hua Yu
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Patent number: D1021220Type: GrantFiled: July 15, 2021Date of Patent: April 2, 2024Assignee: Radiant Opto-Electronics CorporationInventors: Cheng-Ang Chang, Guo-Hao Huang, Chun-Yi Sun, Chih-Hung Ju, Pin-Tsung Wang