Patents by Inventor Cheng-Hung Chang

Cheng-Hung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210333496
    Abstract: An optical transceiver module and an optical cable module using the same are provided. The optical transceiver module: a substrate; at least one optical receiving device connected to the substrate; a plurality of optical transmitting devices connected to the substrate, wherein the optical transmitting devices comprise a plurality of first optical transmitting devices and a plurality of second optical transmitting devices, and the optical transmitting devices are misaligned to each other.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 28, 2021
    Inventors: Chun-Yang CHANG, Cheng-Hung LU, Chang-Cherng WU
  • Patent number: 11158314
    Abstract: A voice control device includes a user database, a first image capturing module, a voice command module and a management module. The user database stores first user identification data of a first user account. The first image capturing module captures an environmental image. The voice command module is enabled to receive a voice command for controlling the voice control device. The management module is used to detect whether at least one facial image exists in the environmental image, and detect whether the facial image matches with the first user identification data, and when the facial image matches with the first user identification data, the management module logs in the first user account and enables the voice command module.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: October 26, 2021
    Assignee: PEGATRON CORPORATION
    Inventors: Cheng-Yu Kao, Nien-Chih Wang, Yu-Hung Tseng, Yueh-Fei Chang, Chih-Lun Wang
  • Publication number: 20210320072
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu LEE, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng, Ka Fai Chang
  • Patent number: 11133387
    Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung Chang, Chen-Hua Yu, Chen-Nan Yeh
  • Patent number: 11127704
    Abstract: A semiconductor device includes a substrate and at least one bump structure disposed over the substrate. The at least one bump structure includes a pillar formed of a metal having a lower solderability than copper or a copper alloy to a solder alloy disposed over the substrate. A solder alloy is formed directly over and in contact with an upper surface of the metal having the lower solderability than copper or a copper alloy. The pillar has a height of greater than 10 ?m.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Haw Tsao, Chen-Shien Chen, Cheng-Hung Tsai, Kuo-Chin Chang, Li-Huan Chu
  • Patent number: 11114563
    Abstract: Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Hua Yu
  • Patent number: 11038056
    Abstract: System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. Hsin-Chu, Taiwan
    Inventors: Chen-Hua Yu, Cheng-Hung Chang, Chen-Nan Yeh, Yu-Rung Hsu
  • Publication number: 20210005515
    Abstract: A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T1 at a first end of the opening, and a thickness T2 at a second end of the opening, and R1 is a ratio of T1 to T2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T3 at the first end of the opening, a thickness T4 at the second end of the opening, R2 is a ratio of T3 to T4, and R1 is greater than R2.
    Type: Application
    Filed: September 15, 2020
    Publication date: January 7, 2021
    Inventors: Chen-Hua YU, Cheng-Hung CHANG, Ebin LIAO, Chia-Lin YU, Hsiang-Yi WANG, Chun Hua CHANG, Li-Hsien HUANG, Darryl KUO, Tsang-Jiuh WU, Wen-Chih CHIOU
  • Patent number: 10784162
    Abstract: A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20190288070
    Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.
    Type: Application
    Filed: June 3, 2019
    Publication date: September 19, 2019
    Inventors: Cheng-Hung Chang, Chen-Hua Yu, Chen-Nan Yeh
  • Patent number: 10312327
    Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung Chang, Chen-Hua Yu, Chen-Nan Yeh
  • Patent number: 10242308
    Abstract: The present invention provides a radio frequency identification and sensing device comprising an antenna module, a RFID sensing module, and battery module. The antenna module has a first flexible substrate having an antenna circuit formed thereon. The RFID sensing module comprises a second flexible substrate, a RFID chip, a sensor formed on the second flexible substrate and a memory module formed on the second flexible substrate, wherein the sensor is utilized to detecting an environmental status for generating a plurality of sensing data, and the memory module is utilized to store the plurality of sensing data. The RFID chip is utilized to transfer the plurality of data to a reading device. The battery module is utilized to provide electrical power for operating the RFID sensing module.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 26, 2019
    Assignee: Securitag Assembly Group Co., Ltd
    Inventors: Tian lin Yan, Cheng hung Chang, Way Yu Chen
  • Publication number: 20190067107
    Abstract: A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.
    Type: Application
    Filed: October 23, 2018
    Publication date: February 28, 2019
    Inventors: Chen-Hua YU, Cheng-Hung CHANG, Ebin LIAO, Chia-Lin YU, Hsiang-Yi WANG, Chun Hua CHANG, Li-Hsien HUANG, Darryl KUO, Tsang-Jiuh WU, Wen-Chih CHIOU
  • Patent number: 10166707
    Abstract: The present invention provides an RFID device and manufacturing method. The RFID device comprises a first housing, an antenna module, and a second housing. The antenna module arranged on the first housing comprises a base substrate, and an antenna layer, sticking on an outer surface of the base substrate. The second housing is formed to couple to the first housing by an injection molding process so that the antenna module is arranged between the first and second housings.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 1, 2019
    Assignee: SECURITAG ASSEMBLY GROUP CO., LTD
    Inventors: Cheng hung Chang, Ching Mei Chi, Chun Jun Chuang, Ya Chi Shen, Tian lin Yan
  • Patent number: 10115634
    Abstract: A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20180226506
    Abstract: Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Hua Yu
  • Publication number: 20180169917
    Abstract: The present invention provides an RFID device and manufacturing method. The RFID device comprises a first housing, an antenna module, and a second housing. The antenna module arranged on the first housing comprises a base substrate, and an antenna layer, sticking on an outer surface of the base substrate. The second housing is formed to couple to the first housing by an injection molding process so that the antenna module is arranged between the first and second housings.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 21, 2018
    Applicant: Securitag Assembly Group Co., Ltd
    Inventors: Cheng hung Chang, Ching Mei Chi, Chun Jun Chuang, Ya Chi Shen, Tian lin Yan
  • Publication number: 20180174017
    Abstract: The present invention provides a radio frequency identification and sensing device comprising an antenna module, a RFID sensing module, and battery module. The antenna module has a first flexible substrate having an antenna circuit formed thereon. The RFID sensing module comprises a second flexible substrate, a RFID chip, a sensor formed on the second flexible substrate and a memory module formed on the second flexible substrate, wherein the sensor is utilized to detecting an environmental status for generating a plurality of sensing data, and the memory module is utilized to store the plurality of sensing data. The RFID chip is utilized to transfer the plurality of data to a reading device. The battery module is utilized to provide electrical power for operating the RFID sensing module.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 21, 2018
    Applicant: Securitag Assembly Group Co., Ltd
    Inventors: Tian lin Yan, Cheng hung Chang, Way Yu Chen
  • Patent number: 9935197
    Abstract: Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Hua Yu
  • Publication number: 20170330939
    Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.
    Type: Application
    Filed: July 31, 2017
    Publication date: November 16, 2017
    Inventors: Cheng-Hung Chang, Chen-Hua Yu, Chen-Nan Yeh