Abstract: A flexible dry electrode and the manufacturing method thereof are provided. The electrode has an electroplated uneven surface and at least one hole and is made of porous material.

Abstract: A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-? dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-? dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric and the fully silicided layer.

Abstract: A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

Abstract: Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.

Abstract: The invention provides an ion current measurement device for a tool having an ion source. The ion current measurement device comprises an ion collecting cup and a replaceable liner. The ion collecting cup is disposed in the tool and the ion collecting cup possesses a cup opening facing the ion source. The replaceable liner is disposed in the ion collecting cup and the replaceable liner entirely covers a continuous inner sidewall of the ion collecting cup.

Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

Abstract: A method of performing an ion implantation is provided. A workpiece is installed in the ion implanter. A wafer is provided in a receiving space within an ion implanter. An ion beam is generated by an ion source of the ion implanter. The bombard of the ion beam is blocked and particles generated during or after conducting the step of generating the ion beam are collected by the workpiece.

Abstract: System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

Abstract: A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.

Abstract: An ion beam blocking component suitable for blocking an ion beam generated by an ion source of an ion implanter is provided. The blocking component includes a front plate, a back plate, and a plurality of side plates. The front plate has at least one opening. The back plate is behind the front plate, and has a plurality of grooves formed on one surface thereof facing the front plate. The side plates are connected between the front plate and the back plate, and a receiving space is formed between these plates.

Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-? dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-? dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric and the fully silicided layer.

Abstract: The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type.

Abstract: An ion beam blocking component suitable for blocking an ion beam generated by an ion source of an ion implanter is provided. The blocking component includes a front plate, a back plate, and a plurality of side plates. The front plate has at least one opening. The back plate is behind the front plate, and has a plurality of grooves formed on one surface thereof facing the front plate. The side plates are connected between the front plate and the back plate, and a receiving space is formed between these plates.

Abstract: Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.

Abstract: The present invention relates to an interactive gaming method and apparatus with emotion perception ability, by which not only gestures of a user can be detected and used as inputs for controlling a game, but also physiological attributes of the user such as heart beats, galvanic skin response (GSR), etc., can be sensed and used as emotional feedbacks of the game affecting the user. According to the disclosed method, the present invention further provides an interactive gaming apparatus that will interpret the signals detected by the inertial sensing module and the bio sensing module and use the interpretation as a basis for evaluating the movements and emotions of a user immediately, and then the evaluation obtained by the interactive gaming apparatus is sent to the gaming platform to be used as feedbacks for controlling the game to interact with the user accordingly.

Abstract: A method for reducing particles during ion implantation is provided. The method involves the use of an improved Faraday flag including a beam plate having thereon a beam striking zone comprising a recessed trench pattern on which the ion beam scans to and fro. An ion beam selected from the mass analyzer is blocked by the Faraday flag in a closed position between the mass analyzer and the semiconductor wafer. A beam current of the ion beam impinging on the beam striking zone of the beam plate is measured. After the beam current measurement, the Faraday flag is removed such that the ion beam impinges on the semiconductor wafer.

Abstract: A method for reducing particles during ion implantation is provided. The method involves the use of an improved Faraday flag including a beam plate having thereon a beam striking zone comprising a recessed trench pattern on which the ion beam scans to and fro. An ion beam selected from the mass analyzer is blocked by the Faraday flag in a closed position between the mass analyzer and the semiconductor wafer. A beam current of the ion beam impinging on the beam striking zone of the beam plate is measured. After the beam current measurement, the Faraday flag is removed such that the ion beam impinges on the semiconductor wafer.

Abstract: Disclosed herein are various embodiments of semiconductor devices and related methods of manufacturing a semiconductor device. In one embodiment, a method includes providing a semiconductor substrate and forming a metal silicide on the semiconductor substrate. In addition, the method includes treating an exposed surface of the metal silicide with a hydrogen/nitrogen-containing compound to form a treated layer on the exposed surface, where the composition of the treated layer hinders oxidation of the exposed surface. The method may then further include depositing a dielectric layer over the treated layer and the exposed surface of the metal silicide.

Abstract: An inductively-coupled plasma etch apparatus and a feedback control method thereof are provided. A voltage/current measuring device is connected to an electrostatic chuck of the plasma etching apparatus, so as to measure the RF current, voltage and the phase angle between them on the electrostatic chuck. The ion current and the RF bias voltage are obtained by calculation of the RF current, voltage and the phase angle. Finally, using the obtained ion current and the RF bias voltage to feedback control the RF power generator in order to achieve the desired plasma status.