Patents by Inventor Cheng-Hung Chang
Cheng-Hung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8263462Abstract: A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.Type: GrantFiled: December 31, 2008Date of Patent: September 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ting Hung, Cheng-Hung Chang, Chen-Yi Lee, Chen-Nan Yeh, Chen-Hua Yu
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Publication number: 20120211807Abstract: System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.Type: ApplicationFiled: February 10, 2012Publication date: August 23, 2012Applicant: Taiwan Semiconductor Manufacturing Comapny, Ltd.Inventors: Chen-Hua YU, Cheng-Hung CHANG, Chen-Nan YEH, Yu-Rung HSU
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Publication number: 20120194268Abstract: A differential voltage sensing method for achieving input impedance matching comprises the steps of: providing a first bio-potential signal to a first variable resistor for generating a first signal; providing a second bio-potential signal to a second variable resistor for generating a second signal; differentially amplifying first and second signals for generating a third signal; selecting an operation band of the third signal for generating first and second logic signals; and dynamically adjusting one of the impedances of the first and second variable resistors according to the first and second logic signals, wherein each of the first and second bio-potential signals has a common signal voltage level and a differential signal voltage level.Type: ApplicationFiled: April 16, 2012Publication date: August 2, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Wen Ying CHANG, CHENG HUNG CHANG, YING JU CHEN
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Publication number: 20120083107Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.Type: ApplicationFiled: December 8, 2011Publication date: April 5, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Chen-Hua Yu, Chen-Nan Yeh
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Patent number: 8143114Abstract: System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.Type: GrantFiled: February 15, 2011Date of Patent: March 27, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Cheng-Hung Chang, Chen-Nan Yeh, Yu-Rung Hsu
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Publication number: 20120025313Abstract: A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.Type: ApplicationFiled: October 13, 2011Publication date: February 2, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Yi Lee, Shih-Ting Hung, Chen-Nan Yeh, Chen-Hua Yu
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Patent number: 8106459Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.Type: GrantFiled: May 6, 2008Date of Patent: January 31, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Chen-Hua Yu, Chen-Nan Yeh
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Patent number: 8093883Abstract: The invention provides an ion current measurement device for a tool having an ion source. The ion current measurement device comprises an ion collecting cup and a replaceable liner. The ion collecting cup is disposed in the tool and the ion collecting cup possesses a cup opening facing the ion source. The replaceable liner is disposed in the ion collecting cup and the replaceable liner entirely covers a continuous inner sidewall of the ion collecting cup.Type: GrantFiled: October 7, 2008Date of Patent: January 10, 2012Assignee: United Microelectronics Corp.Inventors: Jui-Fang Chen, Cheng-Hung Chang, Chung-Jung Chen, Chien-Kuo Ko, Chi-Chun Yao
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Patent number: 8063389Abstract: A method of performing an ion implantation is provided. A workpiece is installed in the ion implanter. A wafer is provided in a receiving space within an ion implanter. An ion beam is generated by an ion source of the ion implanter. The bombard of the ion beam is blocked and particles generated during or after conducting the step of generating the ion beam are collected by the workpiece.Type: GrantFiled: March 12, 2009Date of Patent: November 22, 2011Assignee: United Microelectronics Corp.Inventors: Jui-Fang Chen, Cheng-Hung Chang, Chung-Jung Chen, Chih-Ming Yang, Chien-Kuo Ko
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Patent number: 8048723Abstract: A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.Type: GrantFiled: December 5, 2008Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Yi Lee, Shih-Ting Hung, Chen-Nan Yeh, Chen-Hua Yu
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Publication number: 20110223735Abstract: A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.Type: ApplicationFiled: May 9, 2011Publication date: September 15, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: CHEN-HUA YU, YU-RUNG HSU, CHEN-NAN YEH, CHENG-HUNG CHANG
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Publication number: 20110204971Abstract: A differential voltage sensing method for achieving input impedance matching comprises the steps of: providing a first bio-potential signal to a first variable resistor for generating a first signal; providing a second bio-potential signal to a second variable resistor for generating a second signal; differentially amplifying first and second signals for generating a third signal; selecting an operation band of the third signal for generating first and second logic signals; and dynamically adjusting one of the impedances of the first and second variable resistors according to the first and second logic signals, wherein each of the first and second bio-potential signals has a common signal voltage level and a differential signal voltage level.Type: ApplicationFiled: May 21, 2010Publication date: August 25, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Wen Ying CHANG, Cheng Hung Chang, Ying Ju Chen
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Publication number: 20110171805Abstract: System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.Type: ApplicationFiled: February 15, 2011Publication date: July 14, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Cheng-Hung Chang, Chen-Nan Yeh, Yu-Rung Hsu
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Patent number: 7977772Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-? dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-? dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric and the fully silicided layer.Type: GrantFiled: May 11, 2010Date of Patent: July 12, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Cheng-Tung Lin, Cheng-Hung Chang, Hsiang-Yi Wang, Chen-Nan Yeh
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Publication number: 20110118574Abstract: A physiological signal sensing device for examination of human is provided. The physiological signal sensing device includes a light emitting fiber and a light receiving fiber. The light emitting fiber includes a plurality of light emitting portions, wherein the light emitting fiber provides a plurality of sensing beams, and the sensing beams are respectively emitted through the light emitting portions. The light receiving fiber includes a plurality of light receiving portions. The light receiving fiber corresponds to the light emitting fiber. The sensing beams are emitted through the light emitting portions, reflected or refracted by the human. And then the sensing beams are received by the light receiving portions.Type: ApplicationFiled: March 10, 2010Publication date: May 19, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Wen-Ying Chang, Cheng-Hung Chang
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Patent number: 7939889Abstract: A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.Type: GrantFiled: October 16, 2007Date of Patent: May 10, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Yu-Rung Hsu, Chen-Nan Yeh, Cheng-Hung Chang
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Patent number: 7910994Abstract: System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.Type: GrantFiled: October 15, 2007Date of Patent: March 22, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Cheng-Hung Chang, Chen-Nan Yeh, Yu-Rung Hsu
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Publication number: 20100276761Abstract: Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.Type: ApplicationFiled: January 6, 2010Publication date: November 4, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hang Tung, Chin-Hsiang Lin, Cheng-Hung Chang, Sey-Ping Sun
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Publication number: 20100221878Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-? dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-? dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric and the fully silicided layer.Type: ApplicationFiled: May 11, 2010Publication date: September 2, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Cheng-Tung Lin, Cheng-Hung Chang, Hsiang-Yi Wang, Chen-Nan Yeh
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Publication number: 20100213548Abstract: Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.Type: ApplicationFiled: November 13, 2009Publication date: August 26, 2010Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Hua Yu