Patents by Inventor Cheng-Hung Chang

Cheng-Hung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7119404
    Abstract: Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS device performance without substantially degrading PMOS device performance and method for forming the same, the method including providing a semiconductor substrate; forming strained shallow trench isolation regions in the semiconductor substrate; forming PMOS and NMOS devices on the semiconductor substrate including doped source and drain regions; forming a tensile strained contact etching stop layer (CESL) over the PMOS and NMOS devices; and, forming a tensile strained dielectric insulating layer over the CESL layer.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: October 10, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Cheng-Hung Chang, Weng Chang, Chu-Yun Fu
  • Publication number: 20060157776
    Abstract: System and method for improving the process performance of a contact module. A preferred embodiment comprises improving the process performance of a contact module by reducing surface variations of an interlayer dielectric. The interlayer dielectric comprises a plurality of layers, a first layer (for example, a contact etch stop layer 610) protects devices on a substrate from subsequent etching operations, while a second layer (for example, a first dielectric layer 620) covers the first layer. A third layer (for example, a second dielectric layer 630) fills gaps that may be due to the topography of the devices. A fourth layer (for example, a third dielectric layer 640), brings the interlayer dielectric layer to a desired thickness and is formed using a process that yields a very flat surface completes the interlayer dielectric. Using multiple layers permit the elimination of variations (filling gaps and leveling bumps) without resorting to chemical-mechanical polishing.
    Type: Application
    Filed: January 20, 2005
    Publication date: July 20, 2006
    Inventors: Cheng-Hung Chang, Hsiao-Tzu Lu, Chu-Yun Fu, Weng Chang, Shwang-Ming Jeng
  • Publication number: 20060154481
    Abstract: Disclosed herein are various embodiments of semiconductor devices and related methods of manufacturing a semiconductor device. In one embodiment, a method includes providing a semiconductor substrate and forming a metal silicide on the semiconductor substrate. In addition, the method includes treating an exposed surface of the metal silicide with a hydrogen/nitrogen-containing compound to form a treated layer on the exposed surface, where the composition of the treated layer hinders oxidation of the exposed surface. The method may then further include depositing a dielectric layer over the treated layer and the exposed surface of the metal silicide.
    Type: Application
    Filed: January 7, 2005
    Publication date: July 13, 2006
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zhen-Cheng Wu, Cheng-Hung Chang, Yu-Lien Huang, Shwang-Ming Cheng
  • Publication number: 20060049036
    Abstract: A method comprises measuring an RF voltage and ion current at a wafer during a plasma-enhanced deposition process, determining a sputter rate in response to the RF voltage and ion current measurements, detecting an abnormal condition in response to one of the RF voltage and ion current measurements, and sputter rate, and taking a corrective action in response to detecting an abnormal condition.
    Type: Application
    Filed: September 9, 2004
    Publication date: March 9, 2006
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung Chang, Jhi-Cherng Lu, Joung-Wei Liou, Chu-Yun Fu, Weng Chang, Syung-Ming Jang
  • Publication number: 20060024879
    Abstract: A MOSFET device pair with improved drive current and a method for producing the same to selectively introduce strain into a respective N-type and P-type MOSFET device channel region, the method including forming a compressive stressed nitride layer on over the P-type MOSFET device and a tensile stressed nitride layer on the N-type MOSFET device followed by forming a PMD layer having a less compressive or tensile stress.
    Type: Application
    Filed: July 31, 2004
    Publication date: February 2, 2006
    Inventors: Chu-Yun Fu, Cheng-Hung Chang
  • Publication number: 20050260806
    Abstract: Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS device performance without substantially degrading PMOS device performance and method for forming the same, the method including providing a semiconductor substrate; forming strained shallow trench isolation regions in the semiconductor substrate; forming PMOS and NMOS devices on the semiconductor substrate including doped source and drain regions; forming a tensile strained contact etching stop layer (CESL) over the PMOS and NMOS devices; and, forming a tensile strained dielectric insulating layer over the CESL layer.
    Type: Application
    Filed: May 19, 2004
    Publication date: November 24, 2005
    Inventors: Cheng-Hung Chang, Weng Chang, Chu-Yun Fu
  • Patent number: 6383554
    Abstract: There is provided a process and its system for fabricating plasma with feedback control on plasma density. This process uses a heterodyne millimeter wave interferometer as a sensor to measure the plasma density in the process container and the plasma density that is needed in the plasma fabricating process, and then provides real-time information of the measurements to a digital control device which makes numerical calculations and then drives the RF power generator to change the RF output power so as to enable the plasma density in the plasma fabricating process to be close to the expected plasma density. The conventional operation parameter method is to control air pressure, RF power, gas flow quantity, temperature and so on. However, it does not control the plasma parameter that has the most direct influence on the process. Therefore, this method cannot guarantee that, in the process of fabricating wafers, different batches of wafers will be operated under similar process plasma conditions.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: May 7, 2002
    Assignee: National Science Council
    Inventors: Cheng-Hung Chang, Keh-Chyang Leou, Chaung Lin, Yi-Mei Yang, Chuen-Horng Tsai, I. G. Chen