Abstract: A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a substrate comprising an NMOS region and a PMOS region abutting the NMOS region, a first shallow trench isolation (STI) disposed across the PMOS region and the NMOS region, the first STI has a first bottom being slanted from the NMOS region towards the PMOS region. The semiconductor device structure also includes a first fin disposed in the PMOS region, a first source/drain epitaxial feature disposed over the first fin, a second fin disposed in the NMOS region, a second source/drain epitaxial feature disposed over the second fin, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, the first dielectric feature having a portion embedded in the first STI.

Abstract: An integrated inductor is provided. The integrated inductor includes a first winding and a second winding, and has a first end, a second end, and a node. The first winding utilizes the first end and the node as two ends thereof and includes a first coil and a second coil, which do not overlap. The second winding utilizes the second end and the node as two ends thereof and includes a third coil and a fourth coil, which do not overlap. The first coil and the third coil have an overlapping area, and the second coil and the fourth coil have an overlapping area. The first coil is surrounded by the third coil, and the fourth coil is surrounded by the second coil.

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure that includes channel layers, inner spacers disposed between adjacent ones of the channel layers, and a gate structure extending lengthwise in a first direction. A first trench extending lengthwise perpendicular to the first direction is formed, which divides the gate structure into segments. A first isolation feature is deposited in the first trench. The method also includes etching the gate structure and the channel layers to form a second trench extending lengthwise in the first direction. The second trench exposes the inner spacers. A second isolation feature is deposited in the second trench. The second isolation feature intersects the first isolation feature in a top view of the semiconductor device.

Abstract: A slot antenna structure includes an antenna unit and a metal unit. The metal unit is electrically connected to the antenna unit and includes a first slot, a second slot, and a third slot. The first slot has a first length along a direction. The second slot is spaced a first distance apart from the first slot and has a second length along the direction. The third slot is spaced a second distance apart from the second slot and has a third length along the direction. The first slot, the second slot, and the third slot are arranged in sequence along the direction. The first length is greater than the second length, and the third length is greater than the first length.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, wherein the second epitaxial layer has a first dopant concentration, and a third epitaxial layer having sidewalls enclosed by the second epitaxial layer, wherein the third epitaxial layer has a second dopant concentration higher than the first dopant concentration. The semiconductor device structure also includes a source/drain cap layer disposed above and in contact with the second epitaxial layer and the third epitaxial layer, wherein the source/drain cap layer has a third dopant concentration higher than the second dopant concentration, and a silicide layer disposed above and in contact with the source/drain cap layer.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first source/drain epitaxial feature disposed in a first region, and the first source/drain epitaxial feature is asymmetric with respect to a fin. The structure further includes a second source/drain epitaxial feature disposed in the first region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, and a conductive feature disposed over the first and second source/drain epitaxial features and the first dielectric feature.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first side and a second side opposing the first side, a source/drain epitaxial feature disposed adjacent the first side of the substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, and a third epitaxial layer having sidewalls surrounded by and in contact with the second epitaxial layer. The device structure also includes a first silicide layer in contact with the substrate, the first, second, and third epitaxial layers, a first source/drain contact extending through the substrate from the first side to the second side, and a first metal capping layer disposed between the first silicide layer and the first source/drain contact.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first plurality of vertically aligned semiconductor layers disposed over a substrate and a first gate electrode layer surrounding each of the first plurality of vertically aligned semiconductor layers. The first gate electrode layer includes first one or more work function metal layers disposed between adjacent semiconductor layers of the first plurality of vertically aligned semiconductor layers and two first conductive layers disposed on opposite sides of the first one or more work function metal layers. The first conductive layers include a material different from the first one or more work function metal layers. The first gate electrode layer further includes a second conductive layer disposed on the first conductive layers, and the second conductive layer and the first conductive layers include a same material.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes receiving a workpiece comprising a channel region over a substrate, a source/drain feature adjacent the channel region, a gate structure over the channel region, and a dielectric structure over the source/drain feature. The method also includes forming a contact opening penetrating through the dielectric structure to expose the source/drain feature, forming a silicide layer in the contact opening and on the source/drain feature, forming a tungsten-containing layer in the contact opening and on the silicide layer, and forming a conductive layer in the contact opening and on the tungsten-containing layer, where a composition of the conductive layer is different from a composition of the tungsten-containing layer.

Abstract: A source/drain component is disposed over an active region and surrounded by a dielectric material. A source/drain contact is disposed over the source/drain component. The source/drain contact includes a conductive capping layer and a conductive material having a different material composition than the conductive capping layer. The conductive material has a recessed bottom surface that is in direct contact with the conductive capping layer. A source/drain via is disposed over the source/drain contact. The source/drain via and the conductive material have different material compositions. The conductive capping layer contains tungsten, the conductive material contains molybdenum, and the source/drain via contains tungsten.

Abstract: Some implementations described herein provide a semiconductor device having an oxide-filled barrier structure between structures of gate-all-around transistors included in the semiconductor device. The use of the oxide-filled barrier structure may reduce a distance separating nanosheet structures of a p-type metal-oxide semiconductor fin structure and an n-type metal-oxide semiconductor fin structure, broaden an availability of work-function metals for gate structures formed around nanochannels of the p-type metal-oxide semiconductor fin structure and n-type metal-oxide semiconductor structure, and improve a performance of the gate-all-around transistors by reducing miller capacitances of the gate-all-around transistors. Furthermore, the oxide-filled barrier structure may enable the combining of the p-type metal-oxide semiconductor fin structure and the n-type metal-oxide semiconductor fin structure to form a type of integrated circuitry, such as an inverter.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, a stack of nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, an air spacer disposed between the S/D region and the fin base, and a dielectric layer disposed between the air spacer and the fin base.

Abstract: A semiconductor device includes a substrate, two semiconductor fins protruding from the substrate, an epitaxial feature over the two semiconductor fins and connected to the two semiconductor fins, a silicide layer over the epitaxial feature, a barrier layer over the silicide layer, and a metal layer over the barrier layer. The barrier layer includes a metal nitride. Along a boundary between the barrier layer and the metal layer, an atomic ratio of oxygen to metal nitride is about 0.15 to about 1.0.

Abstract: In method of manufacturing a semiconductor device, a source/drain epitaxial layer is formed, one or more dielectric layers are formed over the source/drain epitaxial layer, an opening is formed in the one or more dielectric layers to expose the source/drain epitaxial layer, a first silicide layer is formed on the exposed source/drain epitaxial layer, a second silicide layer different from the first silicide layer is formed on the first silicide layer, and a source/drain contact is formed over the second silicide layer.

Abstract: Nanostructure transistors are formed in a manner that may reduce the likelihood of source/drain region merging in the nanostructure transistors. In a top-down view of a nanostructure transistor described herein, source/drain regions on opposing sides of a nanostructure channel of the nanostructure transistor are staggered such that the distance between the source/drain regions is increased. This reduces the likelihood of the source/drain regions merging, which reduces the likelihood of failures and/or other defects forming in the nanostructure transistor. Accordingly, staggering the source/drain regions, as described herein, may facilitate the miniaturization of semiconductor devices that include nanostructure transistors while maintaining and/or increasing the semiconductor device yield of the semiconductor devices.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes one or more semiconductor layers, an interfacial layer surrounding at least one semiconductor layer of the one or more semiconductor layers, a work function metal disposed over the interfacial layer, and a high-K (HK) dielectric layer disposed between the interfacial layer and the work function metal. The HK dielectric layer includes a first dopant region adjacent to a first interface of the HK dielectric layer and the interfacial layer, wherein the first dopant region comprises first dopants having a first polarity. The HK dielectric layer also includes a second dopant region adjacent to a second interface of the HK dielectric layer and the work function metal, wherein the second dopant region comprises second dopants having a second polarity opposite the first polarity.

Abstract: Some implementations described herein provide a nanostructure transistor including inner spacers between a gate structure and a source/drain region. The inner spacers, formed in cavities at end regions of sacrificial nanosheets during fabrication of the nanostructure transistor, include concave-regions that face the source/drain region. Formation techniques include forming the sacrificial nanosheets and inner spacers to include certain geometric and/or dimensional properties, such that a likelihood of defects and/or voids within the inner spacers and/or the gate structure are reduced.

Abstract: Wavy-shaped epitaxial source/drain structures for multigate devices and methods of fabrication thereof are disclosed herein. An exemplary device includes a first fin and a second fin extending lengthwise along a first direction. The first fin and the second fin each have a non-recessed portion and a recessed portion. A gate extends lengthwise along a second direction that is different than the first direction. The gate wraps the non-recessed portion of the first fin and the non-recessed portion of the second fin. A merged epitaxial source/drain is on the recessed portion of the first fin and the recessed portion of the second fin. A source/drain contact is on the merged epitaxial source/drain. The source/drain contact and the merged epitaxial source/drain have a V-shaped interface therebetween. The source/drain contact extends below tops of the non-recessed portions of the first fin and the second fin.