Patents by Inventor Cheng-Wei Chang

Cheng-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220189825
    Abstract: A semiconductor device includes a substrate, two semiconductor fins protruding from the substrate, an epitaxial feature over the two semiconductor fins and connected to the two semiconductor fins, a silicide layer over the epitaxial feature, a barrier layer over the silicide layer, and a metal layer over the barrier layer. The barrier layer includes a metal nitride. Along a boundary between the barrier layer and the metal layer, an atomic ratio of oxygen to metal nitride is about 0.15 to about 1.0.
    Type: Application
    Filed: February 21, 2022
    Publication date: June 16, 2022
    Inventors: Cheng-Wei Chang, Yu-Ming Huang, Ethan Tseng, Ken-Yu Chang, Yi-Ying Liu
  • Patent number: 11348993
    Abstract: An electronic device includes a flexible substrate and a conductive wire. The flexible substrate includes a first bending region and a side region connected to the first bending region. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. A ratio of a total width of the metal portion disposed in the first bending region to a total width of the metal portion disposed in the side region is in a range from 0.8 to 1.2, and a length of one of the openings in the first bending region is less than or equal to a length of one of the openings in the side region.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: May 31, 2022
    Assignee: InnoLux Corporation
    Inventors: Ya-Wen Lin, Chien-Chih Chen, Yen-Hsi Tu, Cheng-Wei Chang, Shu-Hui Yang
  • Publication number: 20220139707
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
    Type: Application
    Filed: January 18, 2022
    Publication date: May 5, 2022
    Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Hung-Yi Huang, Chun Chieh Wang, Yu-Ting Lin
  • Patent number: 11295956
    Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 5, 2022
    Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
  • Patent number: 11282750
    Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-Wei Chiu
  • Patent number: 11265466
    Abstract: An electronic device with image-capturing functionality is provided. The electronic device includes a device housing, a module substrate, an image-capturing element, a switch unit and a control unit. The module substrate is adapted to be slid between a first substrate position and a second substrate position. The image-capturing element is disposed on the module substrate. The control unit is coupled to the image-capturing element and the switch unit. When the module substrate is in the first substrate position, the switch unit is activated, the switch unit sends a pressed signal, and the control unit deactivates the image-capturing element according to the pressed signal. When the module substrate is in the second substrate position, the switch unit is not activated, and the control unit activates the image-capturing element. The electronic device of the embodiment protects the privacy of the user.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: March 1, 2022
    Assignee: Wistron Corp.
    Inventors: Cheng Hung Chen, Cheng-Wei Chang
  • Patent number: 11257712
    Abstract: A method includes providing a structure that includes a semiconductor substrate, an epitaxial source/drain feature over the semiconductor substrate, and one or more dielectric layers over the epitaxial source/drain feature; etching a hole into the one or more dielectric layer to expose a portion of the epitaxial source/drain feature; forming a silicide layer over the portion of the epitaxial source/drain feature; forming a conductive barrier layer over the silicide layer; and applying a plasma cleaning process to at least the conductive barrier layer, wherein the plasma cleaning process uses a gas mixture including N2 gas and H2 gas and is performed at a temperature that is at least 300° C.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Wei Chang, Yu-Ming Huang, Ethan Tseng, Ken-Yu Chang, Yi-Ying Liu
  • Patent number: 11256228
    Abstract: An electronic device has a method capable of automatically executing angle rotation. A second body is rotatably connected to a first body of the electronic device. A hinge mechanism is disposed between the first body and the second body. The hinge mechanism includes a hinge component, a motor unit, a coupling component and an angle detecting unit. The first body and the second body are connected to the hinge component. The motor unit is electrically connected to a controller of the electronic device. The coupling component is connected between the hinge component and the motor unit. The angle detecting unit is connected to the hinge component or the coupling component to read its rotary angle. The controller drives the motor unit to rotate the hinge component via the coupling component, and the second body can be moved relative to the first body and be fixed at a predetermined position.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: February 22, 2022
    Assignee: Wistron Corporation
    Inventors: Chen-Yi Liang, Cheng-Wei Chang, Che-Wen Liu
  • Publication number: 20220052168
    Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.
    Type: Application
    Filed: December 4, 2020
    Publication date: February 17, 2022
    Inventors: Cheng-Wei Chang, Hong-Ming Wu, Chen-Yuan Kao, Li-Hsiang Chao, Yi-Ying Liu
  • Publication number: 20220052157
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.
    Type: Application
    Filed: January 29, 2021
    Publication date: February 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei CHANG, Shuen-Shin Liang, Sung-Li Wang, Hsu-Kai Chang, Chia-Hung Chu, Chien-Shun Liao, Yi-Ying Liu
  • Patent number: 11232945
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Hung-Yi Huang, Chun Chieh Wang, Yu-Ting Lin
  • Publication number: 20210407925
    Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.
    Type: Application
    Filed: November 17, 2020
    Publication date: December 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei CHANG, Chien-Shun LIAO, Sung-Li WANG, Shuen-Shin LIANG, Shu-Lan CHANG, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG
  • Patent number: 11209050
    Abstract: A contamination-resistant bearing assembly includes an inner ring, an outer ring, a rolling unit, two contamination-resistant internal sleeves and two contamination-resistant external sleeves. The outer ring cooperates with the inner ring to define a bearing space where the rolling unit and the sleeves are disposed. The external sleeves are located at two opposite sides of the internal sleeves which are located at two opposite sides of the rolling unit in an axial direction. Each of the external sleeves includes a metal rigid shell and a sealing member.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: December 28, 2021
    Assignee: THAI DIENG INDUSTRY CO., LTD.
    Inventor: Cheng-Wei Chang
  • Publication number: 20210358804
    Abstract: A method includes providing a structure that includes a semiconductor substrate, an epitaxial source/drain feature over the semiconductor substrate, and one or more dielectric layers over the epitaxial source/drain feature; etching a hole into the one or more dielectric layer to expose a portion of the epitaxial source/drain feature; forming a silicide layer over the portion of the epitaxial source/drain feature; forming a conductive barrier layer over the silicide layer; and applying a plasma cleaning process to at least the conductive barrier layer, wherein the plasma cleaning process uses a gas mixture including N2 gas and H2 gas and is performed at a temperature that is at least 300° C.
    Type: Application
    Filed: May 13, 2020
    Publication date: November 18, 2021
    Inventors: Cheng-Wei Chang, Yu-Ming Huang, Ethan Tseng, Ken-Yu Chang, Yi-Ying Liu
  • Publication number: 20210202399
    Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.
    Type: Application
    Filed: July 31, 2020
    Publication date: July 1, 2021
    Inventors: Cheng-Wei CHANG, Chia-Hung CHU, Kao-Feng LIN, Hsu-Kai CHANG, Shuen-Shin LIANG, Sung-Li WANG, Yi-Ying LIU, Po-Nan YEH, Yu Shih WANG, U-Ting CHIU, Chun-Neng LIN, Ming-Hsi YEH
  • Publication number: 20210105407
    Abstract: An electronic device with image-capturing functionality is provided. The electronic device includes a device housing, a module substrate, an image-capturing element, a switch unit and a control unit. The module substrate is adapted to be slid between a first substrate position and a second substrate position. The image-capturing element is disposed on the module substrate. The control unit is coupled to the image-capturing element and the switch unit. When the module substrate is in the first substrate position, the switch unit is activated, the switch unit sends a pressed signal, and the control unit deactivates the image-capturing element according to the pressed signal. When the module substrate is in the second substrate position, the switch unit is not activated, and the control unit activates the image-capturing element. The electronic device of the embodiment protects the privacy of the user.
    Type: Application
    Filed: February 17, 2020
    Publication date: April 8, 2021
    Inventors: Cheng Hung CHEN, Cheng-Wei CHANG
  • Publication number: 20210098366
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.
    Type: Application
    Filed: April 9, 2020
    Publication date: April 1, 2021
    Inventors: Cheng-Wei Chang, Sung-Li Wang, Yi-Ying Liu, Chia-Hung Chu, Fang-Wei Lee
  • Patent number: 10963713
    Abstract: An electronic device is disclosed. The electronic device includes a wireless module configured to emit a first radar signal and receive a second radar signal, which is the first radar signal reflected by a user; a gravity sensor configured to sense a status of the electronic device to generate a sensing result; and a control unit coupled to the wireless module and the gravity sensor, and configured to control the wireless module to emit the first radar signal when the sensing result conforms to an emitting condition and determine a physiological status of the user according to the second radar signal received by the wireless module.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: March 30, 2021
    Assignee: Wistron Corporation
    Inventors: Chih-Teng Shen, Cheng-Wei Chang
  • Patent number: 10915147
    Abstract: A portable electronic device is provided and includes a first display module, a second display module, a keyboard device, a sensing unit and a control unit. The second display module is pivotally connected to the first display module. The sensing unit is configured to sense a position of the keyboard device relative to the second display module to output a sensing signal. The control unit is configured to control a displaying image of the second display module according to the sensing signal.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: February 9, 2021
    Assignee: WISTRON CORP.
    Inventors: Chen Yi Liang, Keng-Hsien Yang, Hsin Ting Ho, Cheng-Wei Chang, Fang-Wen Liao
  • Publication number: 20210013033
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Hung-Yi Huang, Chun Chieh Wang, Yu-Ting Lin