Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming first and second semiconductor fins in an NMOS region and a PMOS region, respectively, forming a dielectric feature between the first and second semiconductor fins, recessing the first and second semiconductor fins, forming first and second source/drain epitaxial features over the recessed first and second semiconductor fins, respectively, depositing an interlayer dielectric layer over the first and second source/drain epitaxial features, and forming a first opening in the interlayer dielectric layer to expose a first portion of the first source/drain epitaxial feature and a second opening in the interlayer dielectric layer to expose a first portion of the second source/drain epitaxial feature. The first and second openings are separated by a distance that is about 1.5 times to about 2 times a width of the dielectric feature.

Abstract: An electronic device includes a conductive wire having a metal portion with openings. The openings include a first opening and a second opening arranged along a first direction, and the metal portion includes the first to fourth extending portions and the first to fourth joint portions. The first opening is surrounded by the first extending portion, the second extending portion, the first joint portion, and the second joint portion. The second opening is surrounded by the third extending portion, the fourth extending portion, the third joint portion, and the fourth joint portion. Along the first direction, a ratio of a first width sum of widths of the first extending portion, the second extending portion, the third extending portion, and the fourth extending portion to a second width sum of widths of the first joint portion and the third joint portion is in a range from 0.8 to 1.2.

Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

Abstract: In an embodiment, a method includes: forming a first fin and a second fin over a semiconductor substrate; forming an isolation region between the first fin and the second fin, forming the isolation region comprising: depositing an oxide liner along the first fin, the second fin, and the semiconductor substrate, the oxide liner comprising a first upper portion and a first lower portion along the first fin, the first lower portion being between the first upper portion and the semiconductor substrate; thinning the oxide liner; depositing an insulation material over the oxide liner; and recessing the insulation material; and forming a gate structure over the first fin, the second fin, and the isolation region.

Abstract: A semiconductor structure includes an n-type epitaxial source/drain feature (NEPI) and a p-type epitaxial source/drain feature (PEPI) over a substrate, wherein a top surface of the NEPI is lower than a top surface of the PEPI. The semiconductor structure further includes a metal compound feature disposed on the top surface of the NEPI and the top surface of the PEPI. The metal compound feature extends continuously from the top surface of the NEPI to the top surface of the PEPI. The semiconductor structure further includes a contact feature disposed on the metal compound feature and a via structure disposed over the contact feature.

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Abstract: In method of manufacturing a semiconductor device, a source/drain epitaxial layer is formed, one or more dielectric layers are formed over the source/drain epitaxial layer, an opening is formed in the one or more dielectric layers to expose the source/drain epitaxial layer, a first silicide layer is formed on the exposed source/drain epitaxial layer, a second silicide layer different from the first silicide layer is formed on the first silicide layer, and a source/drain contact is formed over the second silicide layer.

Abstract: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.

Abstract: A method for modulating a threshold voltage of a device. The method includes providing a fin extending from a substrate, where the fin includes a plurality of semiconductor channel layers defining a channel region for a P-type transistor. In some embodiments, the method further includes forming a first gate dielectric layer surrounding at least three sides of each of the plurality of semiconductor channel layers of the P-type transistor. Thereafter, the method further includes forming a P-type metal film surrounding the first gate dielectric layer. In an example, and after forming the P-type metal film, the method further includes annealing the semiconductor device. After the annealing, and in some embodiments, the method includes removing the P-type metal film.

Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.

Abstract: Embodiments of the present disclosure provide a method of forming a contact opening using selective ALE operations to remove ILD layer along an upper profile of a source/drain region, and then form a source/drain contact feature having a concave bottom profile with increased contact area.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a substrate comprising an NMOS region and a PMOS region abutting the NMOS region, a first shallow trench isolation (STI) disposed across the PMOS region and the NMOS region, the first STI has a first bottom being slanted from the NMOS region towards the PMOS region. The semiconductor device structure also includes a first fin disposed in the PMOS region, a first source/drain epitaxial feature disposed over the first fin, a second fin disposed in the NMOS region, a second source/drain epitaxial feature disposed over the second fin, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, the first dielectric feature having a portion embedded in the first STI.

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure that includes channel layers, inner spacers disposed between adjacent ones of the channel layers, and a gate structure extending lengthwise in a first direction. A first trench extending lengthwise perpendicular to the first direction is formed, which divides the gate structure into segments. A first isolation feature is deposited in the first trench. The method also includes etching the gate structure and the channel layers to form a second trench extending lengthwise in the first direction. The second trench exposes the inner spacers. A second isolation feature is deposited in the second trench. The second isolation feature intersects the first isolation feature in a top view of the semiconductor device.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, wherein the second epitaxial layer has a first dopant concentration, and a third epitaxial layer having sidewalls enclosed by the second epitaxial layer, wherein the third epitaxial layer has a second dopant concentration higher than the first dopant concentration. The semiconductor device structure also includes a source/drain cap layer disposed above and in contact with the second epitaxial layer and the third epitaxial layer, wherein the source/drain cap layer has a third dopant concentration higher than the second dopant concentration, and a silicide layer disposed above and in contact with the source/drain cap layer.