Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.

Abstract: An operation-indication mode switching structure, a circuit, and a method for operating the same are provided. The operation-indication mode switching structure is disposed on a housing of a device, and includes a switching mechanism that is used to switch multiple operation-indication modes. The switching mechanism is selectively connected with one of multiple signal terminals. When the switching mechanism is manipulated to switch to one of the operation-indication modes, a control unit of the device receives an operation-indication mode switching signal generated by the switching mechanism conducting or circuit-shorting one of the multiple signal terminals. A corresponding operation-indication mode that is a covert mode, a stealth mode, or a normal mode can be determined. The control unit is used to control an indication function of the device according to the operation-indication mode that is switched to.

Abstract: A body-worn camera and an operation method thereof are provided, and the body-worn camera a central processing unit, a video recording module, a turntable, and a main button. The video recording module is electrically connected to the central processing unit. The turntable is electrically connected to the central processing unit. The main button is electrically connected to the central processing unit. After the video recording module completes recording a video, when the central processing unit receives a category mode signal from the turntable and receives a category name confirmation signal from the main button, the central processing unit executes a video tagging program, and the video tagging program saves a corresponding relationship between a category name and the video.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.

Abstract: A composition for promoting defecation includes a cell culture of at least one lactic acid bacterial strain which is substantially free of cells. The least one lactic acid bacterial strain is selected from the group consisting of Lactobacillus salivarius subsp. salicinius AP-32, Bifidobacterium animalis subsp. lactis CP-9, and Lactobacillus acidophilus TYCA06, which are respectively deposited at the Bioresource Collection and Research Center (BCRC) under accession numbers BCRC 910437, BCRC 910645 and BCRC 910813. Also disclosed is a method for promoting defecation, including administering to a subject in need thereof an effective amount of the composition.

Abstract: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.

Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A display device includes: a substrate having display and non-display areas; a first conductive layer including first and second sub-conductive lines; a second conductive layer including third and fourth sub-conductive lines, wherein, in the display area, the first sub-conductive line and the third sub-conductive lines cross from a top view; and a third conductive layer including third conductive lines and corresponding to the non-display area; wherein, corresponding to the non-display area, a portion of a projection of the one of the third conductive lines is overlapped with a portion of a projection of the second sub-conductive line on the substrate, and another portion of the projection of the one of the third conductive lines is overlapped with a portion of a projection of the fourth sub-conductive line on the substrate.

Abstract: A power supply is provided. The power supply includes a power supply circuit and a control circuit. The power supply circuit includes a voltage converter and multiple point-of-load circuits. The voltage converter generates a third voltage according to a first voltage. The load point-of-load circuits generate at least one second voltage and at least one state signal according to the third voltage. The at least one second voltage is suitable for supplying power to a load. The control circuit is coupled to the power supply circuit. The control circuit determines whether a single event latch-up occurs in the power supply circuit according to the at least one state signal. When the single event latch-up occurs in the power supply circuit, the control circuit switches off the power supply circuit to stop generating the at least one second voltage and the at least one state signal.

Abstract: A method for performing adaptive multi-link aggregation dispatching control in multi-link operation architecture and associated apparatus are provided.

Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.

Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.

Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.

Abstract: An apparatus includes a plurality of switches connected in parallel between an input terminal and an output terminal of a power bus, a plurality of current sensing circuits coupled to the plurality of switches, wherein each current sensing circuit is coupled to a corresponding switch, and a plurality of current sharing circuits configured to receive current sensing signals from the plurality of current sensing circuits and generate a plurality of gate drive signals to control the plurality of switches so as to achieve a predetermined current distribution among the plurality of switches.

Abstract: An immersion cooling unit including a cooling tank, a first cooling unit, and a second cooling unit is provided. The cooling tank includes an accommodating portion and a top. The immersion cooling unit is a single-phase cooling unit. The first cooling unit is connected to the cooling tank. The first cooling unit and the second cooling unit are disposed opposite to each other. The second cooling unit includes a cover portion and a connection portion. The cover portion is connected to the top of the cooling tank and covers the accommodating portion. The connection portion is connected to the cover portion and located in the accommodating portion. In addition, an electronic apparatus is further provided.

Abstract: An example circuit includes a loop controller having current phase inputs, a feedback input, a control loop output and a transient event output. The feedback input is adapted to be coupled to an output terminal of a multi-phase power stage. A PWM circuit has a blanking input, a control input and a PWM output, the control input coupled to the control loop output. A phase management circuit has a transient detect input, a PWM input, a blanking output and phase outputs. The transient detect input is coupled to the transient event output. The PWM input is coupled to the PWM output and the blanking output is coupled to the blanking input. Each of the phase outputs is adapted to be coupled to a respective phase of the multi-phase power stage. The phase management circuit is configured to provide a blanking control signal representative of a variable blanking time.

Abstract: An apparatus such as a power converter includes a first flying capacitor operative to store a first flying capacitor voltage; a second flying capacitor operative to store a second flying capacitor voltage; an inductor providing coupling between the first flying capacitor and the second flying capacitor; and a network of switches operative to, in accordance with control signals, produce an output voltage via the first flying capacitor voltage and the second flying capacitor voltage.