Patents by Inventor Cheng-wei Chen

Cheng-wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210066182
    Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 4, 2021
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
  • Publication number: 20210055616
    Abstract: An electronic device is provided. The electronic device includes a substrate, a driving circuit disposed on the substrate, an active region disposed on the substrate, and a wiring group disposed on the substrate and between the driving circuit and the active area. The wiring group includes a first conductive line and a second conductive line. The first conductive line has a first section and a second section electrically connected to the first section and disposed between the first section and the active region. The second conductive line includes a third section and a fourth section electrically connected to the third section and disposed between the third section and the active region. The first section and the second section are not the same layer. The first section and the fourth section are the same layer. The second section and the third section are the same layer.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 25, 2021
    Inventors: Chih-Hao HSU, Chia-Min YEH, Hsieh-Li CHOU, Cheng-Tso CHEN, Hui-Min HUANG, Li-Wei SUNG, Yu-Ti HUANG
  • Patent number: 10930551
    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hsiang-Wei Liu, Tai-I Yang, Chia-Tien Wu, Hai-Ching Chen, Shau-Lin Shue
  • Fan
    Patent number: 10920790
    Abstract: A fan includes a frame, an impeller, and a motor. The impeller is disposed in the frame and includes a hub, a plurality of annular blades, and a plurality of spacers. The annular blades are stacked along an axial direction of the hub and disposed around the outer periphery of the hub. The extension directions of the annular blades are perpendicular to the axial direction of the hub. Each of the spacers is disposed between the two adjacent annular blades. The motor is disposed in the frame and drives the impeller to rotate to induce an airflow. The thickness of each annular blade is smaller than or equals to 0.2 mm.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 16, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Cheng-Wei Chen
  • Publication number: 20210024672
    Abstract: The present disclosure provides a polymer, including a first repeating unit represented by formula (I), a second repeating unit represented by formula (II), and a third repeating unit represented by formula (III). The first repeating unit, the second repeating unit, and the third repeating unit are arranged in an alternating fashion, in a random fashion, or in discrete blocks. The molar ratio of the first repeating unit, the second repeating unit and the third repeating unit is m:n:o, and m:(n+o) is from 60:40 to 85:15. The definitions of a, R1, R2, A?, and R+ are as defined in the specification.
    Type: Application
    Filed: November 21, 2019
    Publication date: January 28, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsuan-Wei LEE, Cheng-Hsiu TSAI, Chiu-Tung WANG, Li-Duan TSAI, Tzu-Ying CHEN
  • Publication number: 20210019274
    Abstract: A USB bridge including a first USB port, a second USB port, a microcontroller, and a host-to-host function circuit is provided. The first USB port is coupled to the first USB host. The second USB port is coupled to the second USB host. The microcontroller is coupled to the first and the second USB ports. The microcontroller communicates with the first and the second USB hosts via the first and the second USB ports, such that the first and the second USB hosts respectively simulate the USB ports of the first and the second USB hosts as virtual COM ports. The host-to-host function circuit is coupled to the microcontroller and configured to perform a host-to-host transmission function by simulating the USB ports as virtual COM ports.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 21, 2021
    Inventors: Tien-Wei YU, Cheng-Sheng CHAN, Chiun-Shiu CHEN
  • Publication number: 20210020449
    Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
  • Publication number: 20210013234
    Abstract: An electronic device is provided. The electronic device includes a substrate, a first gate circuit, a second gate circuit, a signal line, and a shielding layer. The substrate includes a display area and a peripheral area. The first gate circuit is disposed in the peripheral area. The second gate circuit is disposed in the peripheral area. The signal line is coupled between the first gate circuit and the second gate circuit. The signal line includes a specific line segment, and the specific line segment overlaps the display area. The shielding layer is disposed in the display area. The shielding layer overlaps the specific line segment.
    Type: Application
    Filed: June 22, 2020
    Publication date: January 14, 2021
    Inventors: Yu-Che CHANG, Li-Wei SUNG, Cheng-Tso CHEN, Hui-Min HUANG, Chia-Min YEH, Hung-Hsun CHEN
  • Publication number: 20210012110
    Abstract: An object detection apparatus includes a boundary box decision circuit and a processing circuit. The boundary box decision circuit receives lens configuration information of a lens, and refers to the lens configuration information to determine a bounding box distribution of bounding boxes that are assigned to different detection distances with respect to the lens for detection of a target object. The processing circuit receives a captured image that is derived from an output of an image capture device using the lens, and performs object detection upon the captured image according to the bounding box distribution of the bounding boxes.
    Type: Application
    Filed: February 12, 2020
    Publication date: January 14, 2021
    Inventors: Chih-Wei Chen, Pei-Kuei Tsung, Shao-Yi Wang, Hung-Jen Chen, Kuan-Yu Chen, Cheng-Lung Jen
  • Publication number: 20200410949
    Abstract: A display device includes a substrate, a plurality of scan lines and a plurality of data lines. The data lines respectively have a first segment that overlaps one of the scan lines and a second segment that is located between adjacent two of the scan lines. A first segment of a first data line and a first segment of a second data line are separated by a distance Wa. A first segment of a third data line and a first segment of a fourth data line are separated by a distance Wc. A second segment of the first data line and a second segment of the second data line are separated by a distance W1. A second segment of the third data line and a second segment of the fourth data line are separated by a distance W3. The distances Wa, Wc, W1 and W3 have a relationship (W1/Wa)?(W3/Wc).
    Type: Application
    Filed: June 14, 2020
    Publication date: December 31, 2020
    Inventors: Chia-Min Yeh, Hui-Min Huang, Hsieh-Li Chou, Cheng-Tso Chen, Yu-Chien Kao, Li-Wei Sung
  • Publication number: 20200411374
    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hsiang-Wei Liu, Tai-I Yang, Chia-Tien Wu, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 10879203
    Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Chih-Wei Lin, Cheng-Ting Chen, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20200402859
    Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-Wei Chiu
  • Publication number: 20200394803
    Abstract: An image identifying method is applied to a monitoring camera and a monitoring camera system and used to determine whether a target object is a leaving object or a missing object. The image identifying method includes acquiring a foreground region within a monitoring image corresponding to the target object, analyzing whether the target object inside the foreground region conforms to a variant feature, and comparing the foreground region with a reference image for determining the target object belongs to the leaving object or the missing object when the foreground region does not conform to the variant feature.
    Type: Application
    Filed: November 18, 2019
    Publication date: December 17, 2020
    Inventors: Cheng-Chieh Liu, Chia-Wei Chi, I-Lun Chen
  • Patent number: 10868136
    Abstract: Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • Patent number: 10867862
    Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
  • Patent number: 10867900
    Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Li-Han Hsu, Wei-Cheng Wu
  • Patent number: 10860769
    Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Katherine Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Yi Chen, Ke-Wei Su, Chung-Kai Lin, Lester Chang, Min-Chie Jeng
  • Patent number: 10861692
    Abstract: A method includes receiving a carrier with a plurality of wafers inside; supplying a purge gas to an inlet of the carrier; extracting an exhaust gas from an outlet of the carrier; and generating a health indicator of the carrier while performing the supplying of the purge gas and the extracting of the exhaust gas.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jen-Ti Wang, Chih-Wei Lin, Fu-Hsien Li, Yi-Ming Chen, Cheng-Ho Hung
  • Patent number: 10854780
    Abstract: A light emitting device including a light emitting unit and a phosphor resin layer is provided. The light emitting unit has a top surface and a bottom surface opposite to each other. Each of the light emitting units includes two electrodes. The two electrodes are disposed on the bottom surface. The phosphor resin layer is disposed on the top surface of the light emitting unit. One side of the phosphor resin layer has a mark. One of the two electrodes is closer to the mark with respect to the other one of the two electrodes.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: December 1, 2020
    Assignee: Genesis Photonics Inc.
    Inventors: Cheng-Wei Hung, Chin-Hua Hung, Xun-Xain Zhan, Chuan-Yu Liu, Yun-Chu Chen, Yu-Feng Lin