Patents by Inventor Cheng-wei Chen

Cheng-wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200176566
    Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.
    Type: Application
    Filed: October 8, 2019
    Publication date: June 4, 2020
    Inventors: Cheng-Yi PENG, Ting TSAI, Chung-Wei HUNG, Jung-Ting CHEN, Ying-Hua LAI, Song-Bor LEE, Bor-Zen TIEN
  • Publication number: 20200161412
    Abstract: An electronic device includes a flexible substrate and a conductive wire. The flexible substrate includes a first bending region and a side region connected to the first bending region. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. A ratio of a total width of the metal portion disposed in the first bending region to a total width of the metal portion disposed in the side region is in a range from 0.8 to 1.2, and a length of one of the openings in the first bending region is less than or equal to a length of one of the openings in the side region.
    Type: Application
    Filed: October 17, 2019
    Publication date: May 21, 2020
    Inventors: Ya-Wen Lin, Chien-Chih Chen, Yen-Hsi Tu, Cheng-Wei Chang, Shu-Hui Yang
  • Patent number: 10659097
    Abstract: A testing system includes: a bilinear polarized antenna for receiving and dividing a circularly polarized radio wave associating with a horizontal and a vertical polarization path of an object-to-be-tested into a first and a second high frequency signal; a phase retarder for delaying a phase of the first high frequency signal by 90 degrees to form a first high frequency signal with a phase delay of 90 degrees; a power splitter for receiving or synthesizing the first high frequency signal with the phase delay of 90 degrees and the second high frequency signal; and a high frequency signal transceiver for measuring power of the first high frequency signal with the phase delay of 90 degrees and the second high frequency signal and determining states of the horizontal and vertical polarization paths of the object-to-be-tested based on the power. Therefore, the testing system can speed up testing of the object-to-be-tested.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 19, 2020
    Inventors: Bo-Siang Fang, Kuan-Ta Chen, Ying-Wei Lu, Chia-Chu Lai, Cheng-Tsai Hsieh
  • Publication number: 20200152795
    Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 14, 2020
    Inventors: Cheng-Ta WU, Cheng-Wei CHEN, Shiu-Ko JANGJIAN, Ting-Chun WANG
  • Publication number: 20200154457
    Abstract: Examples pertaining to improvement on user equipment (UE) uplink latency in wireless communications are described. When an apparatus is in a special mode, a processor of the apparatus transmits to a network a request for permission to perform an uplink (UL) transmission for a plurality of times. The processor then receives from the network a grant. In response to receiving the grant, the processor performs the UL transmission to the network. In transmitting the request for the plurality of times, the processor transmits the request for the plurality of times at a frequency higher than a frequency at which the request to perform UL transmissions is transmitted to the network when the apparatus is in a normal operational mode.
    Type: Application
    Filed: October 2, 2019
    Publication date: May 14, 2020
    Inventors: Chiao-Chih Chang, Chien-Liang Lin, Jen-Hao Hsueh, Cheng-Che Chen, Sheng-Yi Ho, I-Wei Tsai, Zhen Jiang, Vincent Yang
  • Patent number: 10651142
    Abstract: A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Hsiung Lu, Chen-Shien Chen, Chen-En Yen, Cheng-Jen Lin, Chin-Wei Kang, Kai-Jun Zhan
  • Patent number: 10651358
    Abstract: A light emitting device package structure includes a substrate, a circuit layer structure, a light emitting device, a first redistribution layer, a conductive connector, a second redistribution layer, and a chip. The circuit layer structure is disposed over the substrate, and the circuit layer structure includes a first circuit layer. The light emitting device is disposed over the circuit layer structure and is electrically connected with the first circuit layer. The first redistribution layer is disposed over the light emitting device and includes a second circuit layer and a conductive contact contacting the second circuit layer. The conductive connector connects the first circuit layer and the second circuit layer. The second redistribution layer is disposed over the first redistribution layer and includes a third circuit layer contacting the conductive contact. The chip is disposed over the second redistribution layer and is electrically connected with the third circuit layer.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 12, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Pei-Wei Wang, Cheng-Ta Ko, Yu-Hua Chen, De-Shiang Liu, Tzyy-Jang Tseng
  • Patent number: 10646741
    Abstract: A weight training equipment with an ultrasonic sensor assembly including a transmitter unit, a receiver unit, a case and the support. The case is rotatably supported upon the support to expose the transmitter and the receiver upwardly. A freely rotatable pin unit is selectively inserted into the hole of the corresponding weight block of the weight training equipment to have its reflection surface downwardly face the sensor assembly. A distance between the pin unit and the sensor assembly during exercise can be measure by ultrasound transmitted from the transmitter unit toward the pin unit and further reflected by the reflection surface and received by the receiver unit.
    Type: Grant
    Filed: January 13, 2018
    Date of Patent: May 12, 2020
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Cheng-Pang Chen, Chang-Wei Kuo, Yi-Chung Teng
  • Publication number: 20200139204
    Abstract: The present invention discloses a badminton racket, which includes a frame, a grip, a cap and a shaft. The grip includes a gripping portion, a sleeved portion, and a fastening element connected to the gripping portion. The sleeved portion has a first top surface and a first opening. The fastening element is connected to the first top surface, and the fastening element extends from the first opening to the inside of the gripping portion. The cap is sleeved onto the sleeved portion and has a second top surface and a second opening. There is a spacing length between the first top surface and the second top surface, and the cap has a cap length. The ratio of the spacing length to the cap length is between 0.39 and 0.83. One end of the shaft is connected to the frame, and another end is inserted into the fastening element.
    Type: Application
    Filed: October 4, 2019
    Publication date: May 7, 2020
    Inventors: Shu-Jung Chen, Tzu-Wei Wang, Hsin-Chen Wang, Cheng-Yu Chang
  • Publication number: 20200129646
    Abstract: A radioactive labeled long-acting peptide-targeting pharmaceutical and production method, in which the peptide targeted pharmaceutical is firstly dissolved in a solution, followed by labeling the radioactive at a high temperature, and the dosage of the pharmaceutical with radioactive labeling is expected to be reduced and labeling efficiency is improved, and no further purification by filtration is required, which shortens the preparation process and reduces personnel exposure in the working environment. The radioactive labeled long-acting peptide-targeting pharmaceutical can increase the specific binding capacity of tumors and reduce the non-specific accumulation in normal tissues. It can be applied to the field of tumor and nuclear medicine for diagnosis and treatment of tumors and/or tumor metastases with efficacy and precision treatment.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Ming-Hsin Li, Chih-Hsien Chang, Su-Jung Chen, Shih-Ying Lee, Sheng-Nan Lo, Ming-Wei Chen, Yuan-Ruei Huang, Chun-Fang Feng, Shih-Wei Lo, Cheng-Hui Chuang
  • Patent number: 10636847
    Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 28, 2020
    Assignee: Apple Inc.
    Inventors: Cheng-Ho Yu, Chin-Wei Lin, Shyuan Yang, Ting-Kuo Chang, Tsung-Ting Tsai, Warren S. Rieutort-Louis, Shih-Chang Chang, Yu Cheng Chen, John Z. Zhong
  • Publication number: 20200125782
    Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 23, 2020
    Inventors: Katherine Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Yi Chen, Ke-Wei Su, Chung-Kai Lin, Lester Chang, Min-Chie Jeng
  • Publication number: 20200118989
    Abstract: A light emitting device package structure includes: a substrate structure including a substrate and a first circuit layer, the substrate having a first surface, the first circuit layer over the first surface; a chip over the substrate structure and electrically connected to the first circuit layer; a conductive connector over the substrate structure and electrically connected to the first circuit layer; a redistribution structure over the conductive connector, the redistribution structure including a first redistribution layer and a second redistribution layer over the first redistribution layer, the first redistribution layer including a second circuit layer electrically connected to the first circuit layer and a conductive contact in contact with the second circuit layer, the second redistribution layer including a third circuit layer in contact with the conductive contact; and a light emitting device over the redistribution structure and electrically connected to the third circuit layer.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 16, 2020
    Inventors: Pei-Wei WANG, Cheng-Ta KO, De-Shiang LIU, Yu-Hua CHEN
  • Patent number: 10622509
    Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 14, 2020
    Assignee: Ingentec Corporation
    Inventors: Ya-Li Chen, Chi-Ming Wang, Chia-Wei Tu, Cheng-Yu Chung, Hsiang-An Feng
  • Patent number: 10622510
    Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: April 14, 2020
    Assignee: Ingentec Corporation
    Inventors: Ya-Li Chen, Chi-Ming Wang, Chia-Wei Tu, Cheng-Yu Chung, Hsiang-An Feng
  • Publication number: 20200105654
    Abstract: A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.
    Type: Application
    Filed: June 21, 2019
    Publication date: April 2, 2020
    Inventors: Ling-Wei Li, Cheng-Lin Huang, Min-Tar Liu, Fu-Kang Chiao, Matt Chou, Chun-Yen Lo, Che-Jung Chu, Wen-Ming Chen, Kuo-Chio Liu
  • Publication number: 20200098889
    Abstract: Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • Patent number: 10600891
    Abstract: A method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate, forming a spacer layer on the substrate surrounding the fin mandrel, forming a wetting layer on each of the sidewalls of the fin mandrel, forming a fin layer on each of the wetting layers, removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tze-Chiang Chen, Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung
  • Patent number: 10596571
    Abstract: A sample processing kit including a centrifugal microfluidic component and a collection component detachably fitted into the microfluidic component is provided. Upon the application of the sample processing kit, target molecules or cells may be separated and collected by the collection component for further experimentation.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: March 24, 2020
    Assignee: National Taiwan University
    Inventors: Andrew Man Chung Wo, Chen-Lin Chen, Cheng-Wei Yang, Wei-Fan Hsu
  • Publication number: 20200078478
    Abstract: A PSMA targeting peptide derivative for radiotherapy, which is a structural molecule developed for diagnosis or treatment of prostate cancer, as prostate-specific membrane antigen (PSMA) is a protein present on the surface of healthy prostate cells, which is often at a high level of expression on the surface of prostate cancer cells, and the molecular composition of PSMA inhibitor is mainly composed of glutamic acid, urea and lysine, in addition to the linker of the present invention, PSMA inhibitor can be combined with a chelating agent and truncated Evans Blue, which can be labeled with radionuclides Ga-67, Ga-68, In-111, Lu-177, Cu-64 or Y-90, used for image analysis and analysis of human prostate cancer tumor pattern as a new PSMA targeting peptide receptor radionuclide therapy (PRRT), and which has a longer half-life in vivo and is featured by specific binding of PSMA for radiotherapy diagnosis or treatment.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 12, 2020
    Inventors: Ming-Hsin Li, Ming-Wei Chen, Shin-Min Wang, Shih-Wei Lo, Chun-Fang Feng, Cheng-Hui Chuang, Sheng-Nan Lo