Abstract: Additive manufacturing (AM) methods and devices for high-melting-point materials are disclosed. In an embodiment, an additive manufacturing method includes the following steps. (S1) Slicing a three-dimensional computer-aided design model of a workpiece into multiple layers according to shape, thickness, and size accuracy requirements, and obtaining data of the multiple layers. (S2) Planning a forming path according to the data of the multiple layers and generating computer numerical control (CNC) codes for forming the multiple layers. (S3) Obtaining a formed part by preheating a substrate, performing a layer-by-layer spraying deposition by a cold spraying method, and heating a spray area to a temperature until the spraying deposition of all sliced layers is completed. (S4) Subjecting the formed part to a surface modification treatment by a laser shock peening method.

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

Abstract: Methods include receiving at least one electronic device including a sensor or an emitter, placing a cover over the sensor or emitter, placing the electronic device, including the cover, into a transfer mold system, encapsulating the electronic device with charge material, and removing a portion of the encapsulating charge material and the cover to expose the sensor or emitter to the environment.

Abstract: A display panel and a display device are provided. The display panel includes a first display area and a second display area, the first display area is provided with a plurality of first pixel repeating units disposed in array, and the second display area is provided with a plurality of second pixel repeating units disposed in array, wherein a quantity of the first light-emitting units included in the first pixel repeating unit is equal to a quantity of the second light-emitting units included in the second pixel repeating unit, and an area of the first pixel repeating unit is smaller than an area of the second pixel repeating unit.

Abstract: The present disclosure provides an electronic device and a display panel. The display panel includes a transition display region and a transparent display region. First pixel driving circuits are placed in the transition display region. Dummy pixel driving circuits are placed in the transition display region. One of the dummy pixel driving circuit is adjacently placed within a predetermined distance from at least one side of the first pixel driving circuits arranged along the second direction. This could reduce the environment difference between the pixel driving circuit close to the light sensing region and the pixel driving circuit inside the transition display region and thus reduce the luminance difference between the first display pixels controlled by the pixel driving circuit close to the light sensing region and the first display pixels controlled by the pixel driving circuit inside the transition display region.

Abstract: A central routing function (CRF) comprises back-to-back user agent application that receives a request for a call route list from a network element, wherein the request comprises a destination telephone number, a list generation application that obtains the call route list from the prioritized call route lists stored in the non-transitory memory based on the destination telephone number, wherein the call route list comprises a plurality of addresses, a pseudo domain name service (DNS) application that translates each address in the call route list into an Internet Protocol (IP) address, in which the back-to-back user agent application attempts to terminate a call using the IP address in the call route list, and in which the CRF platform is implemented in a software container.

Abstract: The present invention utilizes a high-speed intensive mixer in a fluidizing-type, solid-phase, neutralization reactor to blend solid-state alkali hydroxide with any humic acid sources. The final product is a dry humic acid salt. The purpose of this innovative method is to eliminate a series of complicated unit operations commonly employed by the traditional process. These removed steps may include dissolving caustic soda, mixing in a paste-like formation, extrusion, granulation, drying, and grinding, etc. The invention contributes to a simplified flowsheet, resulting in sharply reduced equipment investment, plant space, and labor and energy costs. All of these factors coupled with increased productivity will drastically lower the overall production cost. Also, the reduction of dust pollution will greatly minimize the impact in environmental protection and safety issues.

Abstract: A die including a first contact with a first shape (e.g., ring-shaped) and a second contact with a second shape (e.g., cylindrical shaped) different from the first shape. The first contact has an opening that extends through a central region of a surface of the first contact. A first solder portion is coupled to the surface of the first contact and the first solder portion has the first shape. A second solder portion is coupled to a surface of the second contact and the second solder portion has the second shape. The first solder portion and the second solder portion both have respective points furthest away from a substrate of the die. These respective points of the first solder portion and the second solder portion are co-planar with each other such that a standoff height of the die remains consistent when coupled to a PCB or an electronic component.

Abstract: A heat dissipation assembly is disclosed and includes a fan, a vapor chamber and a heat dissipation fin set. The fan includes a fan frame, an impeller and a fan cover. The impeller is disposed on the fan frame and accommodated in an accommodation space. The impeller includes plural metal blades and a hub, and the plural metal blades are radially arranged on the periphery of the hub to form a dense-metal-blade impeller. The fan cover is assembled with the fan frame to form an outlet, and the fan cover includes an inlet. The vapor chamber includes an upper plate and a lower plate assembled with each other. The upper plate or the lower plate is connected to the fan cover, and the vapor chamber and the fan cover are coplanar. The heat dissipation fin set is connected to the lower plate and spatially corresponding to the outlet.

Abstract: A memory device, a semiconductor device and a manufacturing method of the memory device are provided. The memory device includes first, second and third stacking structures, first and second channel structures, a gate dielectric layer, a switching layer, and first and second gate structures. The first, second and third stacking structures are laterally spaced apart from one another, and respectively comprise a conductive layer, an isolation layer and a channel layer. The third stacking structure is located between the first and second stacking structures. The first channel structure extends between the channel layers in the first and third stacking structures. The second channel structure extends between the channel layers in the second and third stacking structures. The gate dielectric layer and the first gate structure wrap around the first channel structure. The switching layer and the second gate structure wrap around the second channel structure.

Abstract: The present application discloses a display panel and a display device. The display panel includes substrate, a plurality of pixel driving circuits, and a light-shielding layer. By disposing the light-shielding layer in a transition display region of the display panel, disposing the light-shielding layer between the substrate and an active layer of each of transistors of the pixel driving circuits, and configuring an orthographic projection of light-shielding portions on the substrate to cover an orthographic projection of overlapping portions on the substrate, the light-shielding layer can shield infrared light emitted by the transmitting sensor, thereby preventing the transistors from an interference of the infrared light.

Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

Abstract: A method of forming a memory structure includes the following steps. A CMOS circuitry is formed over a semiconductor substrate. A bit line array is formed to be electrically connected to the CMOS circuitry. A memory array is formed over the bit line array. The memory array is formed by forming a word line stack, and forming first and second sets of stacked memory cells. The word line stack is formed on the bit line array and has a first side surface and a second side surface. The first sets of stacked memory cells are formed along the first side surface. The second sets of stacked memory cells are formed along the second side surface, wherein the second sets of stacked memory cells are staggered from the first sets of stacked memory cells. A source line array is formed over the memory array and electrically connected to the CMOS circuitry.

Abstract: Provided is a display device. The display device includes: a first functional layer, a display panel, and a second functional layer. The display panel is disposed on the first functional layer and is defined with a first display region and a second display region. The second display region includes a light transmitting region. The second functional layer is disposed on the display panel. The display device further includes a first film layer, provided with a plurality of opaque or translucent particles arranged irregularly at a position corresponding to the light transmitting region of the second display region. The display device can alleviate the diffraction problem of the camera under panel (CUP) technology of a full screen.

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, an interfacial layer, and a gate electrode. The source region and the drain region are respectively disposed on two opposite ends of the insulating layer. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The interfacial layer is sandwiched between the channel layer and the ferroelectric layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: An electronic device includes an indoor positioning tag and an indoor positioner. The indoor positioning tag includes a gravity sensor. The indoor positioning tag determines whether to start to transmit a wireless signal according to the acceleration magnitude, the acceleration direction, and the duration of acceleration change detected by the gravity sensor, and adjusts the frequency of the transmission interval of the wireless signal.

Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.

Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride (HF) and ammonia (NH3).

Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.