Patents by Inventor Cheng Yang

Cheng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230328996
    Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Inventors: Tsu Ching Yang, Feng-Cheng Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Chung-Te Lin
  • Publication number: 20230327024
    Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang, Feng-Cheng Yang, Neil Quinn Murray
  • Patent number: 11785779
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes multiple alternately stacked insulating layers and gate members. A core structure is disposed in the stacked structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. The present disclosure also provides a method for fabricating the semiconductor structure.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: October 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Jiang, Sheng-Chih Lai, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20230309464
    Abstract: A crop recipe optimization method includes placing crops in an incubator, taking a plurality of images of the crops for measuring crop growth, obtaining a growth score from the plurality of images of the crop, generating, based on the obtained growth score and yield information of the crops, an optimized crop recipe from an artificial intelligence (AI) algorithm, and applying the optimized crop recipe to growing crops in a farm. The plurality of images are associated with one or more crop recipes, and each of the one or more crop recipes represents a set of environmental parameters inside the incubator.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 5, 2023
    Inventors: Song Jin CHNG, Akileshwaran UTHAYAKUMAR, Jing BAI, Cheng Yang, Nicholas THAM, Mun Ji LOW
  • Patent number: 11776602
    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11777004
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a first inter-layer dielectric (ILD) layer formed over the fin structure. The FinFET device structure includes a gate structure formed in the first ILD layer, and a first S/D contact structure formed in the first ILD layer and adjacent to the gate structure. The FinFET device structure also includes a first air gap formed on a sidewall of the first S/D contact structure, and the first air gap is in direct contact with the first ILD layer.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan Lee, I-Wen Wu, Chen-Ming Lee, Jian-Hao Chen, Fu-Kai Yang, Feng-Cheng Yang, Mei-Yun Wang, Yen-Ming Chen
  • Publication number: 20230309299
    Abstract: A memory device includes a dielectric substrate, an interlayer structure, a plurality of channel pillars, a plurality of charge storage structures, a plurality of slit structures and an assistance structure. The dielectric substrate includes an array region and an iso region aside the array region. The interlayer structure is disposed in the array region and the iso region. The channel pillars penetrate through the interlayer structure in the array region. The charge storage structures are disposed between the interlayer structure and the plurality of channel pillars. The slit structures are disposed between the plurality of channel pillars, penetrate through the interlayer structure in the array region, and divide the interlayer structure into a plurality of blocks. The assistance structure is arranged in the iso region. The assistance structure includes at least one dummy slit structure having an extension direction different from an extension direction of the plurality of slit structures.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Applicant: MACRONIX International Co., Ltd.
    Inventor: Chin-Cheng Yang
  • Patent number: 11769820
    Abstract: Methods and devices formed thereof that include a fin structure extending from a substrate and a gate structure is formed over the fin structure. An epitaxial feature is formed over the fin structure adjacent the gate structure. The epitaxial feature can include a hollow region (or dielectric filled hollow region) in the epitaxial source/drain region. A selective etching process is performed to remove at least a portion of an epitaxial region having a second dopant type to form the hollow area between the first epitaxial portion and the third epitaxial portion.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20230299196
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a source region and a drain region arranged over and/or within a substrate. Further, a shallow trench isolation (STI) structure is arranged within the substrate and between the source and drain regions. A gate electrode is arranged over the substrate, over the STI structure, and between the source and drain regions. A portion of the gate electrode extends into the STI structure such that a bottommost surface of the portion of the gate electrode is arranged between a topmost surface of the STI structure and a bottommost surface of the STI structure.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 21, 2023
    Inventors: Yuan-Cheng Yang, Yun-Chi Wu, Shih-Jung Tu
  • Publication number: 20230299939
    Abstract: A method of generating randomness by public participation may comprise: communicating with the commodity devices to execute a protocol comprising a setup phase, a contribution phase and a result-generation phase, wherein: in the setup phase, parameters are initialized, a verifiable delay function is setup, and the parameters are published; the contribution phase is divided into at least one first stage, published parameters are provided, random values are received, and a Merkle tree root and Merkle tree audit paths are published in each of the first stage; and the result-generation phase is divided into at least one second stage of the same number as that of the first stage, each second stage is dedicated to one of the first stage ahead of the second stage for a period, and in each second stage, computation is performed to generate a result of randomness which is published.
    Type: Application
    Filed: January 19, 2023
    Publication date: September 21, 2023
    Applicant: National Taiwan University
    Inventors: Hsun LEE, Yuming HSU, Jing-Jie WANG, Hao Cheng YANG, Yu-Heng CHEN, Yih-Chun HU, Hsu-Chun HSIAO
  • Publication number: 20230294347
    Abstract: A method for producing a polyester film is provided. The method includes a resin alloy master batch preparation step and a film forming step. The resin alloy master batch preparation step includes melting and kneading a high temperature resistant resin material and a polyester resin material with a twin-screw granulator, and then forming a plurality of resin alloy master batches. In the resin alloy master batch preparation step, a twin-screw temperature of the twin-screw granulator is between 250° C. and 320° C., and a twin-screw rotation speed of the twin-screw granulator is between 300 rpm and 800 rpm. The film forming step includes melting and extruding the resin alloy master batches with to form a polyester film. The polyester film includes a heat resistant layer formed of the plurality of resin alloy master batches so that the heat resistant layer includes the high temperature resistant resin material and the polyester resin material.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Inventors: Wen-Cheng YANG, TE-CHAO LIAO, HAO-SHENG CHEN, Chien-Chih LIN
  • Publication number: 20230298503
    Abstract: Provided are a method and an apparatus for gray scale measurement. The method may include: a first part of gray scale data of an LED screen is collected when the LED screen is displaying an image; a type of a chip used for driving the LED screen is determined; and a second part of gray scale data of the LED screen is predicted based on the type of the chip and the first part of gray scale data.
    Type: Application
    Filed: October 19, 2020
    Publication date: September 21, 2023
    Inventors: Yue ZHANG, Hongchun CONG, Cheng YANG
  • Publication number: 20230298997
    Abstract: A routing pattern is provided. The routing pattern includes a first routing region, a second routing region and an interconnection region. The first routing region includes a plurality of first conductive lines extending along a first direction. The plurality of first conductive lines has a first pitch along a second direction perpendicular to the first direction. The second routing region includes a plurality of second conductive lines extending along the first direction. The plurality of second conductive lines has a second pitch along the second direction, and the second pitch is approximately equal to the first pitch. The interconnection region includes two body parts and a connecting part connecting to the body parts. The body parts are disposed separately along the first direction. A width of the connecting part along the second direction is smaller than a width of the body parts along the second direction.
    Type: Application
    Filed: March 17, 2022
    Publication date: September 21, 2023
    Inventors: Chin-Cheng YANG, Yun-Chu LIN
  • Publication number: 20230292972
    Abstract: A debris cleaning mechanism and a cleaning device, comprising a driving mechanism, a transmission mechanism, and a debris scraping mechanism. The transmission mechanism comprises a gear box, and the gear box is connected to the driving mechanism by means of an input shaft and connected to the debris scraping mechanism by means of an output shaft; the debris scraping mechanism comprises a debris scraping body, and the output shaft is in transmission connection with the debris scraping body to drive the debris scraping body to move; the debris scraping body is provided with a first and/or a second debris scraping strip. The cleaning device comprises a debris barrel, a debris barrel cover, the debris cleaning mechanism, and a cover opening mechanism; when a rack of the transmission mechanism moves to a preset position along the axial direction of the debris barrel, the cover opening mechanism is pushed to move.
    Type: Application
    Filed: June 25, 2021
    Publication date: September 21, 2023
    Applicant: Beijing Roborock Technology Co., Ltd.
    Inventors: Xing LI, Zhimin YANG, Yungen QIN, Cheng YANG, Guangzhong LUO, Ping LUO, Liang QIAO
  • Publication number: 20230291938
    Abstract: A method for searching an AD insertion position includes following steps: S1. identifying a human body area in a video image; S2. identifying a blank wall area in the video image; and S3. determining the AD insertion position in the blank wall area in the video image, so that the AD insertion position intersects the human body area. A method for automatically inserting an advertisement AD in a video includes following steps: determining an AD insertion position in the video by searching a product AD insertion position based on deep learning, and inserting the AD on the position. Through the method, an appropriate position for an AD can be automatically searched on a blank wall part in the video. In addition, the inserted AD can be presented in the video in a natural way, and thereby avoiding or reducing the impact of AD insertion on impression of the video.
    Type: Application
    Filed: October 30, 2022
    Publication date: September 14, 2023
    Inventors: Pak Kit Lam, Cheng Yang
  • Publication number: 20230290861
    Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 14, 2023
    Inventors: Tzu-Hsiang Hsu, Ting-Yeh Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11754691
    Abstract: A target measurement device is provided. The target measurement device includes a fixing ring, a main body, and a transceiver. The fixing ring has a first surface. The main body is over the first surface of the fixing ring. The transceiver is coupled to the main body. The transceiver is at least movable between a center of the fixing ring to an edge of the fixing ring from a top view perspective. A method for measuring a target is also provided.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pradip Girdhar Chaudhari, Che-Hui Lee, Chih-Cheng Wei, Wen-Cheng Yang, Chyi-Tsong Ni
  • Patent number: 11758236
    Abstract: Disclosed are a control method for focus movement on an EPG user interface and a display device. The method includes: displaying a television broadcast program on a display screen; receiving an instruction for displaying an EPG user interface, and displaying the EPG user interface on the display screen in response to the instruction; and receiving an instruction for indicating the movement of a focus along a channel arrangement direction in the EPG user interface, and in response to the instruction, determining a new position to which the focus moves in a target television channel according to the position of a pre-selected reference broadcast program, so as to control the focus to move to a target broadcast program corresponding to the new position.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: September 12, 2023
    Assignee: Hisense Visual Technology Co., Ltd.
    Inventors: Cheng Yang, Mengyuan Li
  • Patent number: 11753512
    Abstract: A flame-retardant polyester film and a method for manufacturing the same are provided. The flame-retardant polyester film includes a physically recycled polyester resin and a chemically recycled polyester resin. The physically recycled polyester resin is formed by a plurality of physically recycled polyester chips. The chemically recycled polyester resin is formed by a plurality of chemically recycled polyester chips and mixed with the physically recycled polyester resin. The plurality of chemically recycled polyester chips further includes chemically recycled electrostatic pinning polyester chips. The chemically recycled electrostatic pinning polyester chips contain electrostatic pinning additives, and the electrostatic pinning additives are metal salts. Expressed in percent by weight based on a total weight of the polyester film, a content of the electrostatic pinning additives in the polyester film is between 0.005% and 0.1% by weight.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: September 12, 2023
    Assignee: NAN YA PLASTICS CORPORATION
    Inventors: Wen-Cheng Yang, Te-Chao Liao, Chia-Yen Hsiao, Hao-Sheng Chen
  • Patent number: 11758181
    Abstract: An encoding method is performed by an encoding apparatus, and the encoding method includes a step in which an image of an object captured by a camera in a plurality of frames of a moving image is analyzed and it is determined whether camera parameters relating to an intrinsic matrix of the camera are invariable, a step in which, when the camera parameters are invariable, six parameters representing destinations of three points for a projective transformation unit of the image of the object are generated, and a homography matrix is generated on the basis of the six parameters, and a step in which projective transformation is performed on the projective transformation unit of the image of the object using the homography matrix, and a prediction signal of the image of the object is generated on the basis of the result of the projective transformation.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: September 12, 2023
    Assignees: NIPPON TELEGRAPH AND TELEPHONE CORPORATION, Inter-University Research Institute Corporation Research Organization Of Information And Systems
    Inventors: Seishi Takamura, Gene Cheung, Cheng Yang