Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.

Abstract: A black polyester film and a method for manufacturing the same are provided. The black polyester film includes a physically recycled polyester resin and a chemically recycled polyester resin. The physically recycled polyester resin is formed by a plurality of physically recycled polyester chips. The chemically recycled polyester resin is formed by a plurality of chemically recycled polyester chips and mixed with the physically recycled polyester resin. The plurality of chemically recycled polyester chips further include chemically recycled electrostatic pinning polyester chips. The chemically recycled electrostatic pinning polyester chips contain electrostatic pinning additives, and the electrostatic pinning additives are metal salts. Expressed in percent by weight based on a total weight of the polyester film, a content of the electrostatic pinning additives in the polyester film is between 0.005% and 0.1% by weight. The black polyester film further includes a black additive.

Abstract: A sequence-to-sequence summarizer receives source content to be summarized and determines whether the source content has a size that meets the size threshold. If so, the source content is divided into sections and the sequence-to-sequence summarizer generates a summary for each section. The summaries for each section are merged into a document summary and surfaced for user interaction.

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.

Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: The present invention provides an image sensing device and an image sensing method. The image sensing device comprises an image sensing array and an image processing circuit. The image sensing array obtains a first frame for a test object, and the first frame comprises a plurality of first pixel values. The image processing circuit analyzes the first frame, and generate an overexposure area for the first pixel values greater than a first threshold in the first frame. Then, the image sensor array obtains a second frame for the overexposure area, and the second frame comprises a plurality of second pixel values. The image processing circuit performs a detection processing on all the first pixel values in the first frame, which retains the first pixel values outside of the overexposure area in the first frame, and replaces the first pixel values in the overexposure area with the second pixel values.

Abstract: Embodiments of the present disclosure provide a method, an electronic device, and a computer program product for grouping objects in a data management system. The method includes: detecting operation parameters of at least two of a plurality of objects in a data management system, and determining a rate of correlation between the at least two objects based on the detected operation parameters, wherein the rate of correlation indicates a degree of correlation between the at least two objects. The method further includes: comparing the determined rate of correlation with a predetermined threshold, and determining, based on the comparison of the determined rate of correlation with the predetermined threshold, grouping of the at least two objects. With this method, objects with a high degree of correlation are logically grouped together, so that a user can manage objects in batches in an efficient manner during object management, thus improving the system performance.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a source region and a drain region arranged over and/or within a substrate. Further, a shallow trench isolation (STI) structure is arranged within the substrate and between the source and drain regions. A gate electrode is arranged over the substrate, over the STI structure, and between the source and drain regions. A portion of the gate electrode extends into the STI structure such that a bottommost surface of the portion of the gate electrode is arranged between a topmost surface of the STI structure and a bottommost surface of the STI structure.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric material.

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A Janus membrane exhibiting sides with different properties and methods of fabricating such a Janus membrane. The membrane comprises a polymer material lacking polar functional groups. One side of the membrane is masked during atomic layer deposition (ALD). ALD is utilized to deposit a conformal coating on an exposed side of the membrane.

Abstract: An apparatus and method for physical vapor deposition includes a magnetron having a plurality of electromagnets disposed between a base and a magnetic conductive plate. The magnetron includes a plurality of individually controlled electromagnets between a base and an electromagnetic plate. The magnetron controls the polarity and strength of current supplied to the respective electromagnets to generate magnetic fields that confine electrons to areas near a target material within the deposition chamber.

Abstract: A polyester film for laser embossing and a method for manufacturing the same are provided. The polyester film for laser embossing is made from a recycled polyester material, and includes a base layer and a skin layer. The skin layer is disposed on at least one surface of the base layer. The skin layer is formed from a first polyester composition. The first polyester composition includes regenerated polyethylene terephthalate as a main component and at least one component selected from 1,4-butanediol, isophthalic acid, neopentyl glycol, 2-methyl-1,3-propanediol, pentanediol, isopentyldiol, adipic acid, and 1,4-cyclohexanedimethanol, so that a melting point of the skin layer ranges from 190° C. to 240° C.

Abstract: A semiconductor device includes a substrate having a first region and a second region of opposite conductivity types, an isolation feature over the substrate, a first fin protruding from the substrate in the first region, a first epitaxial feature over the first fin, a second fin protruding from the substrate in the second region, and a second epitaxial feature over the second fin. The isolation feature includes a first portion disposed on sidewalls of the first fin, a second portion disposed on sidewalls of the second fin, and a third portion located between the first fin and the second fin. The third portion has a thickness larger than the first portion and the second portion.

Abstract: A central routing function (CRF) platform. The CRF platform comprises at least one processor; a non-transitory memory communicatively coupled to the at least one processor that stores a plurality of prioritized international call route lists where each prioritized international call route list associates alternative international communication service carrier routes in a prioritized order with an international telephone number; and a call process application stored in the non-transitory memory that, when executed by the processor, receives a request for a prioritized international call route list from a network element, where the request comprises an international telephone number, pads out the international telephone number received from the network element to form a 15-digit number, looks up a prioritized international route list using the 15-digit number in the non-transitory memory, and sends the prioritized international route list to the network element.

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed adjacent to a metal gate structure (MG), an S/D contact disposed over the S/D feature, and a dielectric layer disposed over the S/D contact, where the S/D feature and the S/D contact are separated from the MG by a first air gap, where the dielectric layer partially fills the first air gap, and where a bottom portion of a bottom surface of the S/D contact is separated from a top portion of the S/D feature by a second air gap that is connected to the first air gap.