Patents by Inventor Cheng Yang

Cheng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

Air gap formation between gate spacer and epitaxy structure

Patent number: 11855097

Abstract: A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define a void therebetween. The second spacer seals the void between the first spacer and the epitaxy structure. The dielectric residue is in the void and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has a silicon-to-nitrogen atomic ratio higher than a silicon-to-nitrogen atomic ratio of the lower portion of the dielectric residue.

Type: Grant

Filed: August 10, 2022

Date of Patent: December 26, 2023

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventors: Bo-Yu Lai, Kai-Hsuan Lee, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
POST GATE DIELECTRIC PROCESSING FOR SEMICONDUCTOR DEVICE FABRICATION

Publication number: 20230411220

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

Type: Application

Filed: July 24, 2023

Publication date: December 21, 2023

Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Cheng Hong Yang, Shih-Hao Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
PHOTOMASK DESIGN CORRECTION METHOD

Publication number: 20230400759

Abstract: A photomask design correction method is provided. The photomask design correction method includes the following steps. A layer information data is provided. An OPC process is performed on the layer information data to obtain a first photomask data. A photomask is fabricated based on the first photomask data. A pattern information data of the photomask is obtained after the photomask is fabricated. The difference between the pattern information data and a database of the OPC process is analyzed. An OPC model of the OPC process is corrected based on the difference to obtain a corrected OPC model. The OPC process is performed using the corrected OPC model on the layer information data to obtain a second photomask data.

Type: Application

Filed: June 9, 2022

Publication date: December 14, 2023

Applicant: United Microelectronics Corp.

Inventors: Min Cheng Yang, Wei Cyuan Lo, Yung-Feng Cheng
Method and apparatus for generating prediction information, and electronic device and medium

Patent number: 11842163

Abstract: Disclosed are a method and apparatus for generating prediction information, and an electronic device and a medium. One embodiment of the method comprises: acquiring at least one input word; generating a word vector of each input word of the at least one input word to obtain a word vector set, wherein the at least one input word is obtained by performing word segmentation on target input text; generating an input text vector on the basis of the word vector set; and on the basis of the input text vector and a user vector, generating prediction information for predicting a user intention, wherein the user vector is obtained on the basis of user historical record information. In this embodiment, prediction information for predicting a user intention is generated, such that the popping up of unnecessary information is reduced. A user can be prevented from being disturbed, thereby improving the user experience.

Type: Grant

Filed: December 9, 2022

Date of Patent: December 12, 2023

Assignee: BEIJING BYTEDANCE NETWORK TECHNOLOGY CO., LTD.

Inventors: Xiaowei Hu, Cheng Yang, Changhu Wang
Memory structure and method of forming the same

Patent number: 11844224

Abstract: A method of forming a memory structure includes the following steps. A CMOS circuitry is formed over a semiconductor substrate. A bit line array is formed to be electrically connected to the CMOS circuitry. A memory array is formed over the bit line array. The memory array is formed by forming a word line stack, and forming first and second sets of stacked memory cells. The word line stack is formed on the bit line array and has a first side surface and a second side surface. The first sets of stacked memory cells are formed along the first side surface. The second sets of stacked memory cells are formed along the second side surface, wherein the second sets of stacked memory cells are staggered from the first sets of stacked memory cells. A source line array is formed over the memory array and electrically connected to the CMOS circuitry.

Type: Grant

Filed: April 26, 2021

Date of Patent: December 12, 2023

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventors: Shih-Hsuan Chien, Meng-Han Lin, Han-Wei Wu, Feng-Cheng Yang
MEMORY CELL, MEMORY ARRAY AND MANUFACTURING METHOD THEREOF

Publication number: 20230397426

Abstract: A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.

Type: Application

Filed: June 5, 2022

Publication date: December 7, 2023

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventors: Yu-Wei Jiang, TsuChing Yang, Sheng-Chih Lai, Feng-Cheng Yang, Chung-Te Lin
METHOD OF FORMING HIGH VOLTAGE TRANSISTOR AND STRUCTURE RESULTING THEREFROM

Publication number: 20230387107

Abstract: A method includes: etching a trench on a surface of a substrate; filling the trench with a dielectric material to form a first isolation region; depositing a patterned mask layer on the substrate, the patterned mask layer comprising an opening exposing the substrate; implanting oxygen into the substrate through the opening to form an implant region; generating a second isolation region from the implant region; and forming a transistor on the substrate. The transistor includes a channel laterally surrounding the second isolation region.

Type: Application

Filed: May 26, 2022

Publication date: November 30, 2023

Inventors: YUAN-CHENG YANG, YUN-CHI WU, TSU-HSIU PERNG, SHIH-JUNG TU, CHENG-BO SHU, CHIA-CHEN CHANG
SEMICONDUCTOR DEVICE

Publication number: 20230387108

Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

Type: Application

Filed: July 31, 2023

Publication date: November 30, 2023

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventors: Chung-Te LIN, Wei-Yuan LU, Feng-Cheng YANG
Semiconductor Device with Air-Spacer

Publication number: 20230387247

Abstract: A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.

Type: Application

Filed: August 8, 2023

Publication date: November 30, 2023

Inventors: Wei-Yang Lee, Feng-Cheng Yang, Chung-Te Lin, Yen-Ming Chen
MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Publication number: 20230389320

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.

Type: Application

Filed: August 9, 2023

Publication date: November 30, 2023

Inventors: Feng-Ching Chu, Feng-Cheng Yang, Katherine H. Chiang, Chung-Te Lin, Chieh-Fang Chen
EPITAXIAL STRUCTURES FOR FIN-LIKE FIELD EFFECT TRANSISTORS

Publication number: 20230387269

Abstract: A semiconductor structure includes a first fin and a second fin protruding from a substrate, isolation features over the substrate to separate the first and the second fins, where a top surface of each of the first and the second fins is below a top surface of the isolation features, inner fin spacers disposed along inner sidewalls of the first and the second fins, where the inner fin spacers have a first height measured from a top surface of the isolation features, outer fin spacers disposed along outer sidewalls of the first and the second fins, where the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height, and a source/drain (S/D) structure merging the first and the second fins, where the S/D structure includes an air gap having a top portion over the inner fin spacers.

Type: Application

Filed: July 26, 2023

Publication date: November 30, 2023

Inventors: Chia-Ta Yu, Sheng-Chen Wang, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
MULTI-LAYER HIGH-K GATE DIELECTRIC STRUCTURE

Publication number: 20230389256

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Type: Application

Filed: August 9, 2023

Publication date: November 30, 2023

Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Yu-Chia Liang, Shih-Hao Lin, Kuei-Lun Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
MANUFACTURING METHOD OF POLYESTER FILM FOR BEING EMBOSSED WITH LASER-ENGRAVED PATTERN

Publication number: 20230383055

Abstract: A manufacturing method of a polyester film for being embossed with a laser-engraved pattern is provided. The manufacturing method includes the steps of forming a polyester material into an unstretched polyester film in a multi-layered co-extrusion manner and stretching the unstretched polyester film in a machine direction and a transverse direction to form a biaxially stretched polyester film. The unstretched polyester film includes a substrate layer and at least one surface layer on the substrate layer. The at least one surface layer includes a polyester-based copolymer that includes 85 to 95 mol % of terephthalic acid residues, 5 to 15 mol % of isophthalic acid, 35 to 74 mol % of ethylene glycol residues, 1 to 15 mol % of neopentyl glycol residues, and 25 to 50 mol % of 1,4-butanediol residues.

Type: Application

Filed: August 14, 2023

Publication date: November 30, 2023

Inventors: TE-CHAO LIAO, Wen-Cheng Yang, WEN-JUI CHENG, Chia-Yen Hsiao
METHOD AND APPARATUS FOR OPEN MICRO-ENVIRONMENT PLANT HEALTH SENSING

Publication number: 20230384279

Abstract: An open micro-environment plant health sensing method includes placing a plurality of sensors in a configurable plant growing base for growing plants, collecting data representing one or more environmental parameters of the plants by the plurality of sensors continuously in real-time, communicating the collected data representing the one or more environmental parameters of the plants through a sensor network mediated by gateways, applying the data representing the one or more environmental parameters to a trained artificial intelligence (AI) engine for correlating micro-environment changes to the plants with one or more plant health parameters, and predicting the one or more plant health parameters for monitoring plant health by the trained AI engine.

Type: Application

Filed: May 16, 2023

Publication date: November 30, 2023

Inventors: Ishwariya VENKATESALU, Song Jin CHNG, Chin Huat Joel LIM, Cheng Yang Nicholas THAM, Mun Ji LOW
SEMICONDUCTOR DEVICE WITH SELF-ALIGNED WAVY CONTACT PROFILE AND METHOD OF FORMING THE SAME

Publication number: 20230387305

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

Type: Application

Filed: August 10, 2023

Publication date: November 30, 2023

Inventors: Chia-Ta Yu, Yen-Chieh Huang, Wei-Yuan Lu, Feng-Cheng Yang, Yen-Ming Chen
Semiconductor device with air-spacer

Patent number: 11830922

Abstract: A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.

Type: Grant

Filed: May 17, 2021

Date of Patent: November 28, 2023

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventors: Wei-Yang Lee, Feng-Cheng Yang, Chung-Te Lin, Yen-Ming Chen
Electronic device and method for improving angle of arrival of a signal

Patent number: 11832146

Abstract: An electronic device includes an indoor positioner and a positioning engine server. The indoor positioner has an antenna array including a plurality of antenna units. The indoor positioner divides the antenna units into multiple antenna unit groups, receives a wireless signal from user equipment at each time point via the antenna unit groups, and calculates a plurality of angles of arrival (AOA) corresponding to the antenna unit groups at each time point. The positioning engine server receives and stores the angles of arrival corresponding to the antenna unit groups at each time point, and filters the angles of arrival according to the angle sizes of the angles of arrival corresponding to the antenna unit groups at each time point stored in an observation period.

Type: Grant

Filed: March 17, 2021

Date of Patent: November 28, 2023

Assignee: QUANTA COMPUTER INC.

Inventors: Po-Shan Kao, Cheng-Yang Tseng, Wan-An Yang, Yan-Cheng Chang
METHODS OF FORMING EPITAXIAL STRUCTURES IN FIN-LIKE FIELD EFFECT TRANSISTORS

Publication number: 20230377987

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

Type: Application

Filed: July 26, 2023

Publication date: November 23, 2023

Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
Memory Array Staircase Structure

Publication number: 20230377624

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

Type: Application

Filed: July 31, 2023

Publication date: November 23, 2023

Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
Hangboard

Patent number: D1006146

Type: Grant

Filed: February 8, 2023

Date of Patent: November 28, 2023

Assignee: Y & Y VERTICAL

Inventor: Cheng Yang

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