Abstract: A resin composition is provided, which includes a first polymer and a second polymer. The first polymer is formed by a reaction of an epoxy resin modified with a first elastic molecular segment and an epoxy resin curing agent. The second polymer is formed by a polymerization of an acrylate modified with a second elastic molecular segment.

Abstract: An ultra-thin solid aluminum electrolytic capacitor includes a case, an element, and a cover. A side of the case is provided with an opening. A flanged clamping portion is provided at the opening. The cover is embedded inside the opening through injection molding to encapsulate the element in the case. The cover includes a base plate, an inner plug, and a sealing side wall. The sealing side wall and the inner plug are vertically provided at an upper end face of the base plate. The inner plug is located at an inner side of the sealing side wall. A gap between an outer peripheral wall of the inner plug and an inner peripheral wall of the sealing side wall forms a groove communicated with the opening. An end face of the inner plug is symmetrically provided with two lead holes.

Abstract: A tissue scaffold is provided. The tissue scaffold includes a textile formed by interweaving a plurality of warp yarns and a plurality of weft yarns. The textile includes a first region and a second region, and the second region is adjacent to the first region. The plurality of warp yarns have different diameters in the first region and the second region. The textile has a plurality of pores, and the size of each of the plurality of pores is between 100 ?m and 800 ?m. A method of manufacturing the aforementioned tissue scaffold is also provided.

Abstract: The present invention provides an electronic device including a receiving circuit, a buffer, an output circuit and a control circuit. The receiving circuit is configured to receive input image data. The buffer is configured to temporarily store the input image data. The output circuit is configured to read the input image data from the buffer to generate output image data. The control circuit is configured to the generate a control signal according to a bit depth of the input image data, to dynamically control a delay time for the output circuit to generate the output image data.

Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.

Abstract: A package structure includes a lead frame, a die, a bonding wire, a first solder and a molding material. The lead frame includes a cavity, and the die is disposed in the cavity. The die includes a substrate, a bonding pad and a backside metal layer. The bonding pad is disposed on a first surface of the substrate. The backside metal layer is disposed on a second surface of the substrate. The bonding wire electrically connects the bonding pad of the die to the lead frame. The first solder is disposed between the backside metal layer and the cavity. The die is soldered onto the lead frame through the first solder. The molding material encapsulates the die and the bonding wire, and also covers the lead frame.

Abstract: The present disclosure describes a semiconductor device having a channel extension structure. The semiconductor device includes a channel structure on a substrate. The channel structure includes a central portion and an end portion. The semiconductor device further includes a gate structure wrapped around the central portion of the channel structure, a source/drain (S/D) structure on the substrate and adjacent to the end portion of the channel structure, and an extension structure between the channel structure and the S/D structure. The extension structure has a first sidewall having a first height and adjacent to the end portion of the channel structure and a second sidewall having a second height and adjacent to the S/D structure greater than the first height.

Abstract: The present invention relates to crystalline forms of a KRas G12C inhibitor and salt thereof. In particular, the present invention relates to crystalline forms of the KRas G12C inhibitor 2-[(2S)-4-[7-(8-chloro-1-naphthyl)-2-[[(2S)-1-methylpyrrolidin-2-yl]methoxy]-6,8-dihydro-5H-pyrido[3,4-d]pyrimidin-4-yl]-1-(2-fluoroprop-2-enoyl)piperazin-2-yl]acetonitrile, pharmaceutical compositions comprising the crystalline forms, processes for preparing the crystalline forms and methods of use thereof.

Abstract: A waterborne autonomous rescue device floats in a body of water and continuously senses an ambient audio in the body of water, and performs voice recognition on the ambient audio to recognize a cry-out-for-help voice, and calculates a direction of an emission source (e.g. a drowning person) that emits the cry-out-for-help voice, and then the waterborne autonomous rescue device will automatically move forward in the direction of the emission source, so that the drowning person can cling to the waterborne autonomous rescue device and be carried to a safe location; a waterborne autonomous rescue system includes the waterborne autonomous rescue device which is further connected to a monitoring device; a monitoring personnel can check the status of the waterborne autonomous rescue device through the monitoring device. When a drowning incident occurs, the monitoring personnel can go to a location of the waterborne autonomous rescue device to carry out subsequent rescue.

Abstract: The present invention relates to crystalline forms of a KRas G12C inhibitor and salt thereof. In particular, the present invention relates to crystalline forms of the KRas G12C inhibitor 2-[(2S)-4-[7-(8-chloro-1-naphthyl)-2-[[(2S)-1-methylpyrrolidin-2-yl]methoxy]-6,8-dihydro-5H-pyrido[3,4-d]pyrimidin-4-yl]-1-(2-fluoroprop-2-enoyl)piperazin-2-yl]acetonitrile, pharmaceutical compositions comprising the crystalline forms, processes for preparing the crystalline forms and methods of use thereof.

Abstract: A flow guiding device in an immersion-cooled chassis of a server comprises at least one deflector located above a chip on a mainboard in the chassis, each deflector comprises a first end for mounting to the mainboard above the chip and a second end inclined away from the mainboard. The first end is immersed in coolant, the second end is higher than the first end; the deflector further comprises a hollow part including multiple through holes for interrupting upward movement vapor bubbles generated by the hot chip, which reduces probability of the vapor bubbles escaping from the coolant liquid and the chassis. A liquid-cooled chassis having the flow guiding device is also disclosed.

Abstract: An edge emitting laser (EEL) device includes a substrate, an n-type buffer layer, a first n-type cladding layer, a grating layer, a spacer layer, a lower confinement unit, an active layer, an upper confinement unit, a p-type cladding layer, a tunnel junction layer and a second n-type cladding layer sequentially arranged from bottom to top. The tunnel junction layer can stop an etching process from continuing to form the second n-type cladding layer into a predetermined ridge structure and converting a part of the p-type cladding layer into the n-type cladding layer to reduce series resistance of the EEL device. Therefore, the optical field and active layer tend to be coupled at the middle of the active layer, the lower half of the active layer can be utilized effectively, and the optical field is near to the grating layer to achieve better optical field/grating coupling efficiency and lower threshold current.

Abstract: Techniques are described herein in which boot firmware validated by secure flash memory validates read-only portions of firmware stored by the firmware or a downloaded image of the read-only portions. The secure flash memory validates a portion of the firmware, which includes the boot firmware and a reference hash of the read-only portions, by comparing a calculated hash of the portion and the reference hash of the portion. The boot firmware initiates a boot of the firmware and validates the read-only portions (or the downloaded image of the read-only portions) by comparing a calculated hash of the read-only portions (or a calculated hash of the downloaded image) and the reference hash of the read-only portions. The boot firmware completes the boot of the firmware based at least on the read-only portions (or the downloaded image) being validated.

Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.

Abstract: A thermally conductive board includes a top metal layer, a bottom metal layer, and an electrically insulating but thermally conductive layer (for simplification hereinafter referred to as “thermally conductive layer”) laminated between the top metal layer and the bottom metal layer. The thermally conductive layer includes a polymer matrix and a thermally conductive filler dispersed in the polymer matrix. The polymer matrix includes an epoxy-based composition consisting of epoxy and chlorine-containing impurities. The chlorine content of the thermally conductive layer is lower than 300 ppm.

Abstract: A backlight module includes a light guide element including first optical microstructures and second optical microstructures. An angle value of an angle of the first optical microstructures is V1. When the second optical microstructures are respectively recessed into or protrude from a bottom surface, a projection of each sub-optical microstructure on a reference plane has a peak point closest or to farthest from a light emitting surface and a first valley point and a second valley point farthest from or closest to the light emitting surface, a height difference between the peak point and the first valley point or the second valley point is ?H, a length difference between the peak point and the first valley point or the second valley point is ?L, and tan?1(?H/?L) is V2, where V2>0 and V2?0.5·V1.

Abstract: Paxos transactions are pipelined in a distributed database formed by a plurality of replica servers. A leader server is selected by consensus of the replicas, and receives a lock on leadership for an epoch. The leader gets Paxos log numbers for the current epoch, which are greater than the numbers allocated in previous epochs. The leader receives database write requests, and assigns a Paxos number to each request. The leader constructs a proposed transaction for each request, which includes the assigned Paxos number and incorporates the request. The leader transmits the proposed transactions to the replicas. Two or more write requests that access distinct objects in the database can proceed simultaneously. The leader commits a proposed transaction to the database after receiving a plurality of confirmations for the proposed transaction from the replicas. After all the Paxos numbers have been assigned, inter-epoch tasks are performed before beginning a subsequent epoch.

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Abstract: A power converter includes an input circuit, a conversion circuit, an output circuit and a processor. The input circuit is configured to receive and detect a front stage power from a front stage device. The conversion circuit is coupled to the input circuit. The output circuit is coupled to the conversion circuit and configured to supply power to a back stage device. The processor is coupled to the input circuit, the conversion circuit and the output circuit. The processor is configured to determine whether the front stage power is stable, and is configured to handshake with the back stage device to confirm a conversion power agreed by the back stage device. The processor is further configured to control the conversion circuit to operate at the conversion power, so as to generate an output power to the back stage device.

Abstract: An apparatus includes one or more processors and logic encoded in one or more non-transitory media for execution by the one or more processors and when executed operable to receive sensor data from a drone that travels around a target object. The logic is further operable to generate, based on the sensor data, a first three-dimensional (3D) reconstruction of the target object. The logic is further operable to estimate a direction of sunlight and a direction of spectral reflection. The logic is further operable to plan a trajectory of sensor capturing positions for the drone to capture images of the target object that reduce an amount of sunlight and an amount of specular reflection.