Abstract: A flow guiding device in an immersion-cooled chassis of a server comprises at least one deflector located above a chip on a mainboard in the chassis, each deflector comprises a first end for mounting to the mainboard above the chip and a second end inclined away from the mainboard. The first end is immersed in coolant, the second end is higher than the first end; the deflector further comprises a hollow part including multiple through holes for interrupting upward movement vapor bubbles generated by the hot chip, which reduces probability of the vapor bubbles escaping from the coolant liquid and the chassis. A liquid-cooled chassis having the flow guiding device is also disclosed.

Abstract: The various embodiments described herein include methods, devices, and systems for reading and writing data from a database table. In one aspect, a method includes: (1) initiating a read transaction to read from a first non-key column of a row in the database table, the database table having a plurality of rows, each row comprising a primary key and a plurality of non-key columns, the initiating including: (a) determining that a write transaction holds a lock on a second non-key column of the row in the database table, and (b) determining that no lock is held on the first non-key column; and (2) in response, concurrently reading data from the first non-key column and writing a new column value to the second non-key column; where each non-key column includes a last-write timestamp that indicates when the last write occurred for the respective non-key column.

Abstract: An electronic device including a metal casing and at least one antenna module is provided. The metal casing includes at least one window. The at least one antenna module is disposed in the at least one window. The at least one antenna module includes a first radiator and a second radiator. The first radiator includes a feeding end, a first ground end joined to the metal casing, a second ground end, a first portion extending from the feeding end to the first ground end, and a second portion extending from the feeding end to the second ground end. A first coupling gap is between the second radiator and the first portion. A second coupling gap is between at least part of the second radiator and the metal casing, and the second radiator includes a third ground end joined to the metal casing.

Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.

Abstract: A method for detecting workpiece based on homogeneous multi-core architecture is illustrate. The method comprises: obtaining detecting images of detecting workpieces; identifying detecting areas of the detecting workpieces in the detecting images; dividing the preset rotation angle to obtain the rotation accuracy and initial rotation angles; based on each of the initial rotation angles, rotating the detecting areas to obtain a rotation area of each of the initial rotation angles; calculating similarity values between each of the rotation areas and a preset qualified area, and determining a largest similarity value as the target similarity value; and when the rotation accuracy is greater than or equal to a preset accuracy, identifying whether the detecting workpiece is a qualified workpiece according to the target similarity value and a preset similarity threshold.

Abstract: A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.

Abstract: A semiconductor device includes a substrate, and a first transistor disposed on the substrate. The first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. A crystal orientation of the first channel layer is <100> or <110>. The magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. The first gate electrode is located over the first channel layer. The first gate dielectric is located in between the first channel layer and the first gate electrode. The first source/drain electrodes are disposed on the first channel layer.

Abstract: A detection device includes a frame, a transport mechanism, detection mechanisms, and a grasping mechanism. The transport mechanism includes a feeding line, a first flow line, and a second flow line arranged in parallel on the frame. The detection mechanisms are arranged on the frame and located on two sides of the transport mechanism. The grasping mechanism is arranged on the frame and used to transport workpieces on the feeding line to the detection mechanisms, transport qualified workpieces to the first flow line, and transport unqualified workpieces to the second flow line.

Abstract: An electronic device and a method for editing a resume are provided. The electronic device includes a display, a transceiver, a storage medium, and a processor. The processor receives personal information through the transceiver, and inputs the personal information into a plurality of item templates to generate an item template with personal information and a blank item template without personal information corresponding to the plurality of item templates. The processor displays the plurality of item templates through the display, and receives a first input operation to add a first item template and a second item template in the plurality of item templates to a resume display area to generate a resume. The processor outputs the resume through the transceiver.

Abstract: A hybrid power conversion circuit includes a high-side switch, a low-side switch, a transformer, a resonance tank, a first switch, a second switch, a first synchronous rectification switch, a second synchronous rectification switch, and a third switch. The resonance tank has an external inductor, an external capacitance, and an internal inductor. The first switch is connected to the external inductor. The second switch and a first capacitance form a series-connected path, and is connected to the external capacitance. The first and second synchronous rectification switches are respectively coupled to a first winding and a second winding. The third switch is connected to the second synchronous rectification switch. When an output voltage is less than a voltage interval, the hybrid power conversion circuit operates in a hybrid flyback conversion mode, and otherwise the hybrid power conversion circuit operates in a resonance conversion mode.

Abstract: An embedded circuit board, made without gas bubbles or significant internal gaps according to a manufacturing method which is provided, includes an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces and a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.

Abstract: A method for production analysis includes: receiving production data at a processor from a plurality of tools spatially arranged within a manufacturing facility; creating a hierarchal topology of the data in the processor, wherein each level of the hierarchal topology is based on a different one of a plurality of static parameters that are selected from a list consisting of: a tool identifier, a batch identifier, and a spatial orientation; displaying, at a user interface implemented by the processor, a first analysis of a first level of the hierarchal topology, wherein the analysis contains parameters related to other levels of the hierarchal topology; receiving, via the user interface, a selection by a user of a first parameter displayed on the first analysis; and updating the user interface to display a second analysis of a second level of the hierarchal topology that is related to the first parameter.

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.

Abstract: The present technology proposes techniques for generating globally coherent timestamps. This technology may allow distributed systems to causally order transactions without incurring various types of communication delays inherent in explicit synchronization. By globally deploying a number of time masters that are based on various types of time references, the time masters may serve as primary time references. Through an interactive interface, the techniques may track, calculate and record data relative to each time master thus providing the distributed systems with causal timestamps.

Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate strip disposed over the substrate. The gate strip includes a high-k layer disposed over the substrate, an N-type work function metal layer disposed over the high-k layer, and a barrier layer disposed over the N-type work function metal layer. The barrier layer includes at least one first film containing TiAlN, TaAlN or AlN.

Abstract: An antenna module includes first to third radiators and a ground radiator. The first radiator includes first and second sections and excites at a first frequency band. An extension direction of the first section, including a feeding end, is not parallel to an extension direction of the second section. The second radiator includes third and fourth sections. The third section extends from an intersection of the first and second sections. The third section excites at a second frequency band. The third radiator is disposed beside the first radiator and away from the second radiator. The ground radiator is disposed on one side of the first, second, and third radiators, and includes a ground end. The fourth section of the second radiator is connected to the third section and the ground radiator. The third radiator is connected to the ground end.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The FinFET device structure also includes a metal silicide layer over the S/D structure, and the metal silicide layer is in contact with the isolation structure.