Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

Abstract: An embedded circuit board, made without gas bubbles or significant internal gaps according to a manufacturing method which is provided, includes an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces and a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.

Abstract: A cart for wafer transportation includes a cart body, a separator disposed between first and second wafer holders, an airtight lock configured to seal the cart body. A wafer transfer system includes a cart including a space for holding a wafer holder, a first workstation configured to load the wafer holder into the space and pressurize the space, and a second workstation configured to depressurize the space and unload the wafer holder from the space, wherein the cart is transportable between the first workstation and the second workstation. A method for transporting wafers includes docking a cart in a workstation; loading a wafer holder into a space of the cart; pressurizing the space to cause a pressure of the space to be greater than an atmospheric pressure; maintaining the pressure of the space at the pressure; and moving the cart carrying the wafer holder away from the workstation.

Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.

Abstract: The present invention relates to crystalline forms of a KRas G12C inhibitor and salt thereof. In particular, the present invention relates to crystalline forms of the KRas G12C inhibitor 2-[(2S)-4-[7-(8-chloro-1-naphthyl)-2-[[(2S)-1-methylpyrrolidin-2-yl]methoxy]-6,8-dihydro-5H-pyrido[3,4-d]pyrimidin-4-yl]-1-(2-fluoroprop-2-enoyl)piperazin-2-yl]acetonitrile, pharmaceutical compositions comprising the crystalline forms, processes for preparing the crystalline forms and methods of use thereof.

Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.

Abstract: A backlight module includes a film, a light guide plate disposed under the film, and a circuit board disposed under the light guide plate and provided with a light-emitting unit. The film includes a single-key transparent area, a light-shielding area disposed around the single-key transparent area, and a side transparent area disposed adjacent to or along an edge of the film. The light guide plate has a first microstructure group and a through hole correspondingly disposed under the single-key transparent area, a second microstructure group correspondingly disposed under the side transparent area, and a light-transmitting area partially correspondingly disposed under the light-shielding area. The light-emitting unit is accommodated in the through hole. A number of microstructures or a light-emitting area of the second microstructure group is greater than a number of microstructures or a light emitting area of the first microstructure group.

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

Abstract: A semiconductor device includes: a substrate; a seed layer disposed on the substrate; a compound semiconductor stack layer disposed on the seed layer; and a source metal layer and a drain metal layer disposed on the compound semiconductor stack layer. The semiconductor device further includes a conductive layer at least partially covering the source metal layer and the drain metal layer, and covering opposing side surfaces of the seed layer and opposing side surfaces of the compound semiconductor stack layer. The conductive layer electrically connects the seed layer and the source metal layer.

Abstract: A vertical cavity surface emitting laser (VCSEL) device includes a substrate, a first mirror layer, a tunnel junction layer, a second mirror layer, an active layer, an oxide layer and a third mirror layer sequentially stacked with one another. The first mirror layer and the third mirror layer are N-type distributed Bragg reflectors (N-DBR), and the second mirror layer is P-type distributed Bragg reflector (P-DBR). The tunnel junction layer is provided for the VCSEL device to convert a part of the P-DBR into N-DBR to reduce the series resistance of the VCSEL device, and the tunnel junction layer is not used as current-limiting apertures. This disclosure further discloses a VCSEL device manufacturing method with the in-situ and one-time epitaxy features to avoid the risk of process variation caused by moving the device into and out from an epitaxial cavity.

Abstract: A method of testing a non-volatile memory (NVM) array includes heating the NVM array to a target temperature, and while the NVM array is heated to the target temperature, programming a subset of the NVM cells to first resistance levels and obtaining a first current distribution, programming the subset of NVM cells to second resistance levels and obtaining a second current distribution, calculating a current threshold level from the first and second current distributions, and for each of the NVM cells, programing the NVM cell to one of the first or second resistance levels, and using the current threshold level to determine a first pass/fail (P/F) status and a second P/F status at the programmed resistance level. A bit error rate (BER) of the NVM array is calculated based on the first and second current distributions and the first and second P/F status of each of the NVM cells.

Abstract: A cart for wafer transportation includes a cart body, a separator disposed between first and second wafer holders, an airtight lock configured to seal the cart body. A wafer transfer system includes a cart including a space for holding a wafer holder, a first workstation configured to load the wafer holder into the space and pressurize the space, and a second workstation configured to depressurize the space and unload the wafer holder from the space, wherein the cart is transportable between the first workstation and the second workstation. A method for transporting wafers includes docking a cart in a workstation; loading a wafer holder into a space of the cart; pressurizing the space to cause a pressure of the space to be greater than an atmospheric pressure; maintaining the pressure of the space at the pressure; and moving the cart carrying the wafer holder away from the workstation.

Abstract: It is checked, using machine learning, whether at least one fail bit in a memory block of a memory is unrepairable, according to a location of the at least one fail bit, and an available repair resource in the memory. When the checking indicates that the at least one fail bit is not unrepairable, it is determined whether a CSP containing constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected. In response to the checking, using the machine learning, indicating that the at least one fail bit is unrepairable, the memory block is marked as unrepairable or the memory is rejected, without making further determinations as to repairability of the memory block.

Abstract: A gas tube, a gas supply system containing the same and a semiconductor manufacturing method using the same are provided. The gas tube includes a porous material body and a resistant sheath surrounding the porous material body. The porous material body has a hollow tube structure and an empty cavity inside the hollow tube structure. The porous material body is hydrophobic and has a plurality of pores therein. The resistant sheath is disposed on the porous material body and surrounds the porous material body. The resistant sheath includes a plurality of holes penetrating through the resistant sheath.

Abstract: A cleaning device includes a supporting mechanism, a clamping mechanism arranged on the supporting mechanism and used to clamp a spray head, a heating mechanism, an adjusting mechanism, and a cleaning mechanism. The heating mechanism, the adjusting mechanism, and the cleaning mechanism are arranged on the supporting mechanism. The heating mechanism is used to heat the spray head clamped by the clamping mechanism. The cleaning mechanism is used to inject cleaning liquid into the spray head, dredge the spray head, and detect the spray head. The adjusting mechanism is used to rotate and adjust a position of the cleaning mechanism to complete different tasks on the spray head.

Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

Abstract: An electronic device includes a dimming structure, a control unit, a plurality of sensors and an angle sensor. The control unit is electrically connected to the dimming structure. The plurality of sensors are electrically connected to the control unit, and output a sensing result based on a plurality of sensing values sensed by the sensors. The angle sensor is electrically connected to the control unit, and senses a rotation angle of the dimming structure. Based on the sensing result and the rotation angle, the control unit outputs a voltage to the dimming structure.

Abstract: A method for removing extraneous content in a first plurality of images, captured at a corresponding plurality of poses and a corresponding first plurality of times, by a first drone, of a scene in which a second drone is present includes the following steps, for each of the first plurality of captured images. The first drone predicts a 3D position of the second drone at a time of capture of that image. The first drone defines, in an image plane corresponding to that captured image, a region of interest (ROI) including a projection of the predicted 3D position of the second drone at a time of capture of that image. A drone mask for the second drone is generated, and then applied to the defined ROI, to generate an output image free of extraneous content contributed by the second drone.

Abstract: A method for performing enhanced preamble puncturing in a wireless communication system and associated apparatus are provided. The wireless communication system may include a first wireless transceiver device having an enhanced preamble puncturing capability, where the first wireless transceiver device is configured to operate in a first transmission bandwidth including one primary and multiple non-primary channels. The method may include: determining at least one interfered channel in at least one of the primary and non-primary channels; and performing the enhanced preamble puncturing on transmission of physical layer (PHY) protocol data units (PPDUs) including transmitting, in the aforementioned at least one interfered channel, at least one first PHY protocol data unit (PPDU) configured to have a lower power than a power of other PPDUs transmitted in other primary or non-primary channels.