Patents by Inventor Cheng Yi

Cheng Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12219258
    Abstract: An anti-shake assembly with reduced size is disclosed which includes a circuit board, a photosensitive chip, and a magnetic component. The circuit board includes a first rigid board, a second rigid board, a plurality of connectors, and a plurality of coils. The first rigid board has a housing space. The second rigid board is movably housed in the housing space. The connectors are flexibly connected between the first rigid board and the second rigid board. The photosensitive chip and the coils are provided on the second rigid board. The magnetic component includes a base and a plurality of magnets. The base includes a central plate and a side plate. The side plate is arranged around a periphery of the central plate to form a housing space. The magnets are provided on the central plate facing the housing space. The magnets are arranged opposite to the coils.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: February 4, 2025
    Assignees: Avary Holding (Shenzhen) Co., Limited., QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD
    Inventors: Cheng-Yi Yang, Qiang Song, Yan-Qiong He, Yao-Cai Li, Biao Li, Zu-Ai Li, Mei-Hua Huang
  • Patent number: 12216407
    Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hsuan Chuang, Po-Sheng Lu, Shou-Wen Kuo, Cheng-Yi Huang, Chia-Hung Chu
  • Patent number: 12215110
    Abstract: Disclosed is a process for the preparation of certain intermediates, e.g. a process for preparing a compound of formula (I) wherein, R1, R2 and X1 are as defined in the description, and which intermediate and processes are useful in the preparation of a BTK inhibitor, such as ibrutinib.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: February 4, 2025
    Assignee: Janssen Pharmaceutica NV
    Inventors: Philip James Pye, Andras Horvath, Cheng Yi Chen, Yuanyuan Yuan, Jinxiong Su, Shuo Wang, Simon Albert Wagschal
  • Patent number: 12218203
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Ling-Yen Yeh, Chi-Wen Liu, Chih-Sheng Chang, Yee-Chia Yeo
  • Publication number: 20250040183
    Abstract: A method includes: forming a stack of semiconductor nanostructures on a semiconductor fin; forming a source/drain opening adjacent the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer; forming a dielectric layer on the source/drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer; removing the other portions of the dielectric layer, exposing the void; forming a source/drain contact opening that extends to and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region; forming a liner layer on exposed surfaces of the source/drain region; and forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surfac
    Type: Application
    Filed: July 28, 2023
    Publication date: January 30, 2025
    Inventors: Chih-Hao CHANG, Wei-Yang LEE, Kuan-Hao CHENG, Cheng-Yi PENG
  • Publication number: 20250029589
    Abstract: An acoustic metasurface structure is configured to absorb sounds. The acoustic metasurface structure comprises a main body, an externally-connecting configuration and an inner configuration. The externally-connecting configuration and the inner configuration are respectively formed inside the main body. An externally-connecting tube of the externally-connecting configuration is in fluid communication with an external environment and an externally-connecting cavity of the externally-connecting configuration. An inner tube of the inner configuration is in fluid communication with the externally-connecting cavity and an inner cavity of the inner configuration. With the externally-connecting configuration and the inner configuration forming a series-type structure in the main body, the acoustic metasurface structure increases an acoustic impedance.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Inventors: JUNG-SAN CHEN, TZU-HUEI KUO, WEI-CHUN WANG, WEN-YANG LO, CHENG-YI WANG
  • Publication number: 20250030763
    Abstract: Throughput is preserved in a distributed system while maintaining concurrency by pushing a commit wait period to client commit paths and to future readers. As opposed to servers performing commit waits, the servers assign timestamps, which are used to ensure that causality is preserved. When a server executes a transaction that writes data to a distributed database, the server acquires a user-level lock, and assigns the transaction a timestamp equal to a current time plus an interval corresponding to bounds of uncertainty of clocks in the distributed system. After assigning the timestamp, the server releases the user-level lock. Any client devices, before performing a read of the written data, must wait until the assigned timestamp is in the past.
    Type: Application
    Filed: June 20, 2024
    Publication date: January 23, 2025
    Inventors: Wilson Cheng-Yi Hsieh, Peter Hochschild
  • Publication number: 20250022766
    Abstract: A semiconductor device includes: a substrate; a seed layer disposed on the substrate; a compound semiconductor stack layer disposed on the seed layer; and a source metal layer and a drain metal layer disposed on the compound semiconductor stack layer. The semiconductor device further includes a conductive layer at least partially covering the source metal layer and the drain metal layer, and covering opposing side surfaces of the seed layer and opposing side surfaces of the compound semiconductor stack layer. The conductive layer electrically connects the seed layer and the source metal layer.
    Type: Application
    Filed: October 1, 2024
    Publication date: January 16, 2025
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsiu-Mei YU, Guang-Yuan JIANG, Cheng-Yi HSIEH, Wei-Chan CHANG, Chang-Sheng LIN
  • Publication number: 20250022668
    Abstract: A multilayer polymer capacitor (MLPC), including a casing, a multilayer core, an electroplated positive terminal, a first electroplated negative terminal, and a second electroplated negative terminal. The casing includes a casing body and a cover plate. The casing body is provided with an accommodating cavity, whose bottom is provided with a through hole. The multilayer core is provided in the accommodating cavity. An anode lead-out part and a cathode lead-out part are provided at two ends of the accommodating cavity, respectively. The electroplated positive terminal and the first electroplated negative terminal are provided on outer side surfaces of two ends of the casing, respectively. The second electroplated negative terminal is provided on an outer bottom surface of the casing, and is electrically connected to the multilayer core.
    Type: Application
    Filed: September 29, 2024
    Publication date: January 16, 2025
    Inventors: CHENG-YI YANG, I-CHU LIN, YUAN-YU LIN, CHIN-TSUN LIN, Qirui CHEN, HSIU-WEN WU
  • Patent number: 12198910
    Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Jen Yang, Yi-Zhen Chen, Chih-Pin Wang, Chao-Li Shih, Ching-Hou Su, Cheng-Yi Huang
  • Publication number: 20250007168
    Abstract: A dual-polarized patch antenna includes a radiator layer, at least one middle layer disposed below the radiator layer, a ground plane layer disposed below the middle layer to provide a reference potential, and a feed layer disposed below the ground plane layer. The radiator layer includes an insulation substrate that has a top surface and a bottom surface, a base patch that is disposed on the bottom surface, and a top patch that is disposed on the top surface, and that is spaced apart from the base patch by a patch distance. The top patch includes a center portion and an annular portion that encircles and is spaced apart from the center portion. The feed layer includes a feed substrate and two feed lines. The two feed lines are arranged substantially perpendicular to each other for feeding electrical signals.
    Type: Application
    Filed: June 27, 2024
    Publication date: January 2, 2025
    Inventors: Cheng-Yi LIN, Meng-Hua TSAI, Wei-Ting LEE, Sin-Siang WANG
  • Publication number: 20240427399
    Abstract: The disclosed technology is directed to a computing device for detecting and preventing melting of a component of the computing device. In some examples, the computing device includes a cable that connects a power supply unit and an add-on card, and a thermal protection controller. Based on a sensor signal from a temperature sensor of the cable, the thermal protection controller determines that a temperature associated with the cable exceeds a threshold temperature. Responsive to determining that the temperature associated with the cable exceeds the threshold temperature, the thermal protection controller causes the power supply unit to cease supplying power to the add-on card by transmitting an overtemperature signal through the cable.
    Type: Application
    Filed: June 26, 2023
    Publication date: December 26, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Wen-Bin Lin, Chao-Wen Cheng, Cheng-Yi Yang, Chien-Wei Chen
  • Publication number: 20240409586
    Abstract: The present invention relates to a novel cyclic peptide carrier in the field of pharmaceutical technology and its various forms, where the cyclic peptide has the general sequence formula P-(X)m-Cys-(Y)n-Cys-(Z)o-P. The invention also encompasses the construction and preparation technology of a composition or formulation formed by the novel cyclic peptide carrier carrying nucleic acids, drugs, or therapeutic agents. Furthermore, it involves a method for effectively delivering nucleic acids to cells, tissues, or organisms using the composition or formulation, as well as its medical applications.
    Type: Application
    Filed: November 16, 2022
    Publication date: December 12, 2024
    Applicant: SUZHOU HEALIRNA BIOTECHNOLOGY CO., LTD.
    Inventors: Lixiang ZHAO, Qingqing Lu, Yawen Fan, Cheng YI, Youzhen Ge, Dan Xia, Hongpeng Hu
  • Patent number: 12167150
    Abstract: An electronic device is provided that determines initial three-dimensional (3D) coordinates of a lighting device. The electronic device controls an emission of light from the lighting device based on control signals. The emitted light includes at least one of a pattern of alternating light pulses or a continuous light pulse. The electronic device controls a plurality of imaging devices to capture a first plurality of images that include information about the emitted light. Based on the determined initial 3D coordinates and the information about the emitted light included in the first plurality of images, the electronic device estimates a plurality of rotation values and a plurality of translation values of each imaging device. Based on the plurality of rotation values and the plurality of translation values, the electronic device applies a simultaneous localization and mapping process for each imaging device, for spatial synchronization of the plurality of imaging devices.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: December 10, 2024
    Assignees: SONY GROUP CORPORATION, SONY CORPORATION OF AMERICA
    Inventors: Brent Faust, Cheng-Yi Liu
  • Patent number: D1061549
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: February 11, 2025
    Assignee: Acer Incorporated
    Inventors: Ching-Yuan Chuang, Chung-Hsien Lee, Cheng-Yi Chang
  • Patent number: D1061550
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: February 11, 2025
    Assignee: Acer Incorporated
    Inventors: Cheng-Yi Chang, Ming-Chun Wu, Ki-Wi Li, Chung-Hsien Lee, Shau-Tsung Hu, Ching-Yuan Chuang
  • Patent number: D1061609
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: February 11, 2025
    Assignee: Acer Incorporated
    Inventors: Cheng-Yi Chang, Ming-Chun Wu, Ki-Wi Li, Chung-Hsien Lee, Shau-Tsung Hu, Ching-Yuan Chuang
  • Patent number: D1061616
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: February 11, 2025
    Assignee: Acer Incorporated
    Inventors: Cheng-Yi Chang, Ming-Chun Wu, Ki-Wi Li, Chung-Hsien Lee, Shau-Tsung Hu, Ching-Yuan Chuang
  • Patent number: D1062759
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: February 18, 2025
    Assignee: Acer Incorporated
    Inventors: Ching-Yuan Chuang, Chung-Hsien Lee, Cheng-Yi Chang
  • Patent number: D1062760
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: February 18, 2025
    Assignee: Acer Incorporated
    Inventors: Cheng-Yi Chang, Ming-Chun Wu, Ki-Wi Li, Chung-Hsien Lee, Shau-Tsung Hu, Ching-Yuan Chuang