Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via.

Abstract: Various embodiments of the present application are directed towards an integrated chip structure. The integrated chip structure includes a bottom electrode over a substrate, a top electrode over the bottom electrode, and a capacitor insulator structure between the bottom electrode and the top electrode. The capacitor insulator structure includes a first dielectric layer, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. The first dielectric layer includes a first dielectric material. The second dielectric layer includes a second dielectric material that is different than the first dielectric material. The second dielectric material is an amorphous solid. The third dielectric layer includes the first dielectric material.

Abstract: A thermally conductive board includes a top metal layer, a bottom metal layer, and an electrically insulating but thermally conductive layer (for simplification hereinafter referred to as “thermally conductive layer”) laminated between the top metal layer and the bottom metal layer. The thermally conductive layer includes a polymer matrix and a thermally conductive filler dispersed in the polymer matrix. The polymer matrix includes an epoxy-based composition consisting of epoxy and chlorine-containing impurities. The chlorine content of the thermally conductive layer is lower than 300 ppm.

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type work function metal; a barrier material over the first p-type work function metal; and a second p-type work function metal over the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal.

Abstract: A backlight module includes a light guide element including first optical microstructures and second optical microstructures. An angle value of an angle of the first optical microstructures is V1. When the second optical microstructures are respectively recessed into or protrude from a bottom surface, a projection of each sub-optical microstructure on a reference plane has a peak point closest or to farthest from a light emitting surface and a first valley point and a second valley point farthest from or closest to the light emitting surface, a height difference between the peak point and the first valley point or the second valley point is ?H, a length difference between the peak point and the first valley point or the second valley point is ?L, and tan?1(?H/?L) is V2, where V2>0 and V2?0.5·V1.

Abstract: A camera device includes a circuit board, a photosensitive element, a first adhesive layer, a lens assembly, and second adhesive layer. The photosensitive element has a photosensitive region and a non-photosensitive region around the photosensitive region. The first adhesive layer is adhesively fixed to the photosensitive element and the circuit board. The lens assembly includes a base and a lens disposed on the base, and the lens has an optical axis. The base includes a bottom wall and an extension member extending from the bottom wall. A limiting surface of the extension member overlaps the non-photosensitive region in a direction along the optical axis. The second adhesive layer has a positioning block and a limiting block. The positioning block is adhesively fixed to the bottom wall and the circuit board, and the limiting block is adhesively fixed to the limiting surface and the non-photosensitive region.

Abstract: Paxos transactions are pipelined in a distributed database formed by a plurality of replica servers. A leader server is selected by consensus of the replicas, and receives a lock on leadership for an epoch. The leader gets Paxos log numbers for the current epoch, which are greater than the numbers allocated in previous epochs. The leader receives database write requests, and assigns a Paxos number to each request. The leader constructs a proposed transaction for each request, which includes the assigned Paxos number and incorporates the request. The leader transmits the proposed transactions to the replicas. Two or more write requests that access distinct objects in the database can proceed simultaneously. The leader commits a proposed transaction to the database after receiving a plurality of confirmations for the proposed transaction from the replicas. After all the Paxos numbers have been assigned, inter-epoch tasks are performed before beginning a subsequent epoch.

Abstract: A integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. The first and third gate are on a first level. The second and fourth gate are on a second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. The first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. The first input pin is electrically coupled to the third gate by the first, second or fourth gate. The first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.

Abstract: A laptop computer including a system host, a modular platform, a rail structure, and at least one tool is provided. The rail structure is disposed at the system host and the modular platform, and the modular platform slides relative to the system host via the rail structure to be assembled to or detached from the system host. The tool is plugged into or out of the system host, and the tool is located on a sliding path of the modular platform when the tool is assembled to the system host.

Abstract: A method for early warning a blind area of a vehicle. In the method, the electronic device obtains at least one target image acquired by at least one camera of the vehicle. The electronic device further determines parameters of at least one target object in each of the at least one target image and a three-dimensional detection frame for each of the at least one target object based on the parameters. The electronic device further obtains a target detection frame of each of the at least one target object in a top view image of a plane where the vehicle is located by projecting the three-dimensional detection frame into the top view image and outputs alert information in response that an overlapped area exists between the target detection frame and a preset blind area of the top view image.

Abstract: A display device, characterized in that the display device includes a first panel, having a first side and a first light shielding layer at a periphery of the first panel, wherein the first light shielding layer has a first edge departing away from the first side; and a second panel, disposed on the first panel, and having a second side adjacent to the first side; wherein the second panel includes a second light shielding layer at a periphery of the second panel; and the second light shielding layer has a second edge departing away from the second side. Wherein a first width is measured from the first side to the first edge along a direction, a second width is measured from the second side to the second edge along the direction, the second width is greater than the first width, and the direction is vertical to the first side.

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type work function metal; a barrier material over the first p-type work function metal; and a second p-type work function metal over the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal.

Abstract: A power converter includes an input circuit, a conversion circuit, an output circuit and a processor. The input circuit is configured to receive and detect a front stage power from a front stage device. The conversion circuit is coupled to the input circuit. The output circuit is coupled to the conversion circuit and configured to supply power to a back stage device. The processor is coupled to the input circuit, the conversion circuit and the output circuit. The processor is configured to determine whether the front stage power is stable, and is configured to handshake with the back stage device to confirm a conversion power agreed by the back stage device. The processor is further configured to control the conversion circuit to operate at the conversion power, so as to generate an output power to the back stage device.

Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.

Abstract: An apparatus includes one or more processors and logic encoded in one or more non-transitory media for execution by the one or more processors and when executed operable to receive sensor data from a drone that travels around a target object. The logic is further operable to generate, based on the sensor data, a first three-dimensional (3D) reconstruction of the target object. The logic is further operable to estimate a direction of sunlight and a direction of spectral reflection. The logic is further operable to plan a trajectory of sensor capturing positions for the drone to capture images of the target object that reduce an amount of sunlight and an amount of specular reflection.

Abstract: A flow guiding device in an immersion-cooled chassis of a server comprises at least one deflector located above a chip on a mainboard in the chassis, each deflector comprises a first end for mounting to the mainboard above the chip and a second end inclined away from the mainboard. The first end is immersed in coolant, the second end is higher than the first end; the deflector further comprises a hollow part including multiple through holes for interrupting upward movement vapor bubbles generated by the hot chip, which reduces probability of the vapor bubbles escaping from the coolant liquid and the chassis. A liquid-cooled chassis having the flow guiding device is also disclosed.

Abstract: The present invention is directed to methods for the asymmetric synthesis of esketamine. The present invention is further directed to key intermediates in the asymmetric esketamine synthesis. In one embodiment, the invention is an asymmetric synthesis of esketamine comprising the conversion of (S)-2?-chloro-2-methoxy-3,4,5,6-5 tetrahydro-[1, 1?-biphenyl]-3-yl carbamate to (S)-2?-chloro-1-isocyanato-6-methoxy-1,2,3,4-tetrahydro-1,1?-biphenyl.

Abstract: The present disclosure for wafer bonding, including forming an epitaxial layer on a top surface of a first wafer, forming a sacrificial layer over the epitaxial layer, trimming an edge of the first wafer, removing the sacrificial layer, forming an oxide layer over the top surface of the first wafer subsequent to removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer.

Abstract: This application is applicable to the field of machine learning technologies and provides a system and a method for target detection. The system includes: a controller and a coprocessor which is in communication connection with the controller. The controller is configured to perform at least some arithmetic operations of a target detection model based on a target image to be detected and/or data sent by the coprocessor. The coprocessor is configured to perform at least some arithmetic operations of the target detection model based on the target image to be detected and/or data sent by the controller. According to the system for target detection, the controller and the coprocessor are utilized to perform some of the arithmetic operations in the target detection model respectively to solve a problem of slow execution speed of target detection task in deployment of the target detection model.