Patents by Inventor Cheng Yi

Cheng Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12007956
    Abstract: The subject matter described herein provides techniques to ensure that queries of a distributed database observe a consistent read of the database without locking or logging. In this regard, next-write timestamps uniquely identify a set of write transactions whose updates can be observed by reads. By publishing the next-write timestamps from within an extendable time lease and tracking a “safe timestamp,” the database queries can be executed without logging read operations or blocking future write transactions, and clients issuing the queries at the “safe timestamp” observe a consistent view of the database as it exists on or before that timestamp. Aspects of this disclosure also provide for extensions, done cheaply and without the need for logging, to the range of timestamps at which read transactions can be executed.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: June 11, 2024
    Assignee: Google LLC
    Inventors: Wilson Cheng-Yi Hsieh, Eric Hugh Veach, Michael James Boyer Epstein, Alexander Lloyd
  • Patent number: 12006954
    Abstract: A filtering device is adapted to be mounted in a fan having a motor cover, a rotary shaft, an impeller combined at the rotary shaft, and a rear protective grill mounting on a mounting base provided on a front end of the motor cover. The filtering device includes an inner ring plate, an outer ring plate, and a filter element. The filter element is sandwiched between the inner ring plate and the outer ring plate, and the inner ring plate and the outer ring plate are coupled between the rear protective grill and the rear protective grill lock ring. The airflow sent out by the rotation of the impeller of the fan will pass through the filter element of the filtering device, achieving the effect of purifying air.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: June 11, 2024
    Assignee: CLUCH ENTERPRISE CO., LTD
    Inventor: Cheng-Yi Shie
  • Patent number: 12009232
    Abstract: In an embodiment, an apparatus comprising: a heater configured to heat a wafer located on a wafer staging area of the heater, the heater comprising a heater shaft extending below the wafer staging area; and a heater lift assembly comprising: a lift shaft configured to move the heater shaft in a vertical direction; a clamp that connects the heater shaft to the lift shaft; and a damper disposed on top of the clamp.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Wen Wu, Chun-Ta Chen, Chin-Shen Hsieh, Cheng-Yi Huang
  • Publication number: 20240175514
    Abstract: A solenoid valve includes a water inlet valve seat, a guide seat, a coil barrel, and a water outlet valve seat. When in an open state, an iron core is moved to close a pressure relief hole via an iron core spring and water pressure, and the diaphragm blocks the water flow of a water inlet via water pressure and the force of a guide spring, so as to achieve a bistable effect. The coil barrel includes two pairs of magnets and a pair of magnetically conductive sheets to form two magnetic routes. The solenoid valve has a simple structure and can be produced easily.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 30, 2024
    Inventor: Cheng-Yi Ma
  • Patent number: 11997066
    Abstract: A data transmission system and method thereof for edge computing are provided. A terminal mobile station international subscriber directory number (MSISDN) and a terminal IP of a target terminal are obtained with a domain name system (DNS) by a device providing communication services from the data transmission system. After data packets are sent to the data transmission system, if the target terminal is in an idle mode, a paging message is sent by a terminal wake-up module to enable the target terminal to return to a connected mode for communication. Before a connection is established between the data transmission system and the target terminal, downlink data packets can be temporarily stored, and the packets can be sent after the target terminal is in the connected mode. A computer readable medium for executing the data transmission method is also provided.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: May 28, 2024
    Assignee: CHUNGHWA TELECOM CO., LTD.
    Inventors: Yi-Hua Wu, Wei-Shan Lu, Kang-Hao Lo, Cheng-Yi Chien, Yueh-Feng Li, Ling-Chih Kao
  • Publication number: 20240172273
    Abstract: Examples pertaining to preamble puncturing negotiation in wireless communications are described. A station (STA) may receive a control frame, and, in response, apply the MRU pattern for one or more transmissions or receptions in a transmission opportunity (TXOP). In the control frame, either a plurality of first reserved bits in a SERVICE field or a plurality of bits in a User Info field are set to indicate a multiple resource unit (MRU) pattern regarding preamble puncturing.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 23, 2024
    Inventors: Cheng-Yi Chang, Kun-Sheng Huang, Yi-Hsuan Chung, Chung-Kai Hsu, Chia-Hsiang Chang, Kai Ying Lu
  • Patent number: 11990510
    Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Ting Tsai, Chung-Wei Hung, Jung-Ting Chen, Ying-Hua Lai, Song-Bor Lee, Bor-Zen Tien
  • Patent number: 11990167
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Jhih Shen, Kuang-I Liu, Joung-Wei Liou, Jinn-Kwei Liang, Yi-Wei Chiu, Chin-Hsing Lin, Li-Te Hsu, Han-Ting Tsai, Cheng-Yi Wu, Shih-Ho Lin
  • Patent number: 11991838
    Abstract: An embedded circuit board made without gas bubbles or significant internal gaps according to a manufacturing method which is here disclosed comprises an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces, a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: May 21, 2024
    Assignees: QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited.
    Inventors: Cheng-Yi Yang, Hao-Wen Zhong, Biao Li, Ming-Jaan Ho, Ning Hou
  • Publication number: 20240162318
    Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.
    Type: Application
    Filed: January 26, 2024
    Publication date: May 16, 2024
    Inventors: Min-Kun DAI, Wei-Gang CHIU, I-Cheng CHANG, Cheng-Yi WU, Han-Ting TSAI, Tsann LIN, Chung-Te LIN
  • Publication number: 20240143560
    Abstract: The various embodiments described herein include methods, devices, and systems for reading and writing data from a database table. In one aspect, a method includes: (1) initiating a read transaction to read from a first non-key column of a row in the database table, the database table having a plurality of rows, each row comprising a primary key and a plurality of non-key columns, the initiating including: (a) determining that a write transaction holds a lock on a second non-key column of the row in the database table, and (b) determining that no lock is held on the first non-key column; and (2) in response, concurrently reading data from the first non-key column and writing a new column value to the second non-key column; where each non-key column includes a last-write timestamp that indicates when the last write occurred for the respective non-key column.
    Type: Application
    Filed: December 21, 2023
    Publication date: May 2, 2024
    Inventors: Wilson Cheng-Yi Hsieh, Alexander Lloyd, Eric Hugh Veach
  • Publication number: 20240147664
    Abstract: A flow guiding device in an immersion-cooled chassis of a server comprises at least one deflector located above a chip on a mainboard in the chassis, each deflector comprises a first end for mounting to the mainboard above the chip and a second end inclined away from the mainboard. The first end is immersed in coolant, the second end is higher than the first end; the deflector further comprises a hollow part including multiple through holes for interrupting upward movement vapor bubbles generated by the hot chip, which reduces probability of the vapor bubbles escaping from the coolant liquid and the chassis. A liquid-cooled chassis having the flow guiding device is also disclosed.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 2, 2024
    Inventors: SUNG TSANG, TSUNG-LIN LIU, YU-CHIA TING, CHENG-YI HUANG, CHIA-NAN PAI
  • Publication number: 20240136441
    Abstract: A semiconductor device includes a substrate, and a first transistor disposed on the substrate. The first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. A crystal orientation of the first channel layer is <100> or <110>. The magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. The first gate electrode is located over the first channel layer. The first gate dielectric is located in between the first channel layer and the first gate electrode. The first source/drain electrodes are disposed on the first channel layer.
    Type: Application
    Filed: February 5, 2023
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ken-Ichi Goto, Cheng-Yi Wu
  • Patent number: 11967906
    Abstract: A hybrid power conversion circuit includes a high-side switch, a low-side switch, a transformer, a resonance tank, a first switch, a second switch, a first synchronous rectification switch, a second synchronous rectification switch, and a third switch. The resonance tank has an external inductor, an external capacitance, and an internal inductor. The first switch is connected to the external inductor. The second switch and a first capacitance form a series-connected path, and is connected to the external capacitance. The first and second synchronous rectification switches are respectively coupled to a first winding and a second winding. The third switch is connected to the second synchronous rectification switch. When an output voltage is less than a voltage interval, the hybrid power conversion circuit operates in a hybrid flyback conversion mode, and otherwise the hybrid power conversion circuit operates in a resonance conversion mode.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: April 23, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Sheng-Yu Wen, Cheng-Yi Lin, Ting-Yun Lu
  • Patent number: 11965833
    Abstract: A detection device includes a frame, a transport mechanism, detection mechanisms, and a grasping mechanism. The transport mechanism includes a feeding line, a first flow line, and a second flow line arranged in parallel on the frame. The detection mechanisms are arranged on the frame and located on two sides of the transport mechanism. The grasping mechanism is arranged on the frame and used to transport workpieces on the feeding line to the detection mechanisms, transport qualified workpieces to the first flow line, and transport unqualified workpieces to the second flow line.
    Type: Grant
    Filed: November 26, 2020
    Date of Patent: April 23, 2024
    Assignees: HONGFUJIN PRECISION ELECTRONICS (ZHENGZHOU) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jing-Zhi Hou, Lin-Hui Cheng, Yan-Chao Ma, Jin-Cai Zhou, Zi-Long Ma, Neng-Neng Zhang, Yi Chen, Chen-Xi Tang, Meng Lu, Peng Zhou, Ling-Hui Zhang, Lu-Hui Fan, Shi-Gang Xu, Cheng-Yi Chao, Liang-Yi Lu
  • Publication number: 20240130050
    Abstract: An embedded circuit board, made without gas bubbles or significant internal gaps according to a manufacturing method which is provided, includes an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces and a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Inventors: Cheng-Yi Yang, Hao-Wen Zhong, Biao Li, Ming-Jaan Ho, Ning Hou
  • Patent number: 11962100
    Abstract: A dual-band antenna module includes a first antenna structure and a second antenna structure. The first antenna structure includes a first insulating substrate, a conductive metal layer, a plurality of grounding supports, and a first feeding pin. The second antenna structure includes a second insulating substrate, a top metal layer, a bottom metal layer, and a second feeding pin. The conductive metal layer is disposed on the first insulating substrate. The grounding supports are configured for supporting the first insulating substrate. The second insulating substrate is disposed above the first insulating substrate. The top metal layer and the bottom metal layer are respectively disposed on a top side and a bottom side of the second insulating substrate. The first frequency band signal transmitted or received by the first antenna structure is smaller than the second frequency band signal transmitted or received by the second antenna structure.
    Type: Grant
    Filed: August 7, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Inpaq electronic Co., Ltd.
    Inventors: Ta-Fu Cheng, Shou-Jen Li, Cheng-Yi Wang, Chih-Ming Su
  • Patent number: 11960830
    Abstract: A method for production analysis includes: receiving production data at a processor from a plurality of tools spatially arranged within a manufacturing facility; creating a hierarchal topology of the data in the processor, wherein each level of the hierarchal topology is based on a different one of a plurality of static parameters that are selected from a list consisting of: a tool identifier, a batch identifier, and a spatial orientation; displaying, at a user interface implemented by the processor, a first analysis of a first level of the hierarchal topology, wherein the analysis contains parameters related to other levels of the hierarchal topology; receiving, via the user interface, a selection by a user of a first parameter displayed on the first analysis; and updating the user interface to display a second analysis of a second level of the hierarchal topology that is related to the first parameter.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: April 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Jonathan Fry, Cheng-Tin Luo, Cheng-Yi Lin, Dureseti Chidambarrao, Jang Sim
  • Publication number: 20240122078
    Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Chang Hsu, Tang-Chun Weng, Cheng-Yi Lin, Yung-Shen Chen, Chia-Hung Lin
  • Patent number: 11953938
    Abstract: The present technology proposes techniques for generating globally coherent timestamps. This technology may allow distributed systems to causally order transactions without incurring various types of communication delays inherent in explicit synchronization. By globally deploying a number of time masters that are based on various types of time references, the time masters may serve as primary time references. Through an interactive interface, the techniques may track, calculate and record data relative to each time master thus providing the distributed systems with causal timestamps.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: April 9, 2024
    Assignee: Google LLC
    Inventors: Peter Hochschild, Alexander Lloyd, Wilson Cheng-Yi Hsieh, Robert Edman Felderman, Michael James Boyer Epstein