Abstract: An embodiment includes a device having nanostructures on a substrate, the nanostructures including a channel region. The device also includes a gate dielectric layer wrapping around each of the nanostructures. The device also includes a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a first n-type work function metal, aluminum, and carbon, the first n-type work function metal having a work function value less than titanium. The device also includes a glue layer on the first work function tuning layer. The device also includes and a fill layer on the glue layer.

Abstract: An inductor device includes a first coil and a second coil. The first coil includes a first connection member and a plurality of first circles. At least two first circles of the first circles are located at a first area, and half of the first circle of the first circles is located at a second area. The second coil includes a second connection member and a plurality of second circles. At least two second circles of the second circles are located at the second area, and half of the second circle of the second circles is located at the first area. The first connection member is coupled to the at least two first circles and the half of the first circle. The second connection member is coupled to the at least two second circles and the half of the second circle.

Abstract: A package structure and a method for forming the same are provided. The package structure includes a first package structure and a second package structure. The first package structure includes a first device formed over a first substrate. The first device includes a first conductive plug connected to a through substrate via (TSV) structure formed in the first substrate. A buffer layer surrounds the first substrate. A first bonding layer is formed over the first substrate and the buffer layer. The second package structure includes a second device formed over a second substrate. A second bonding layer is formed over the second device. A hybrid bonding structure is between the first package structure and the second package structure by bonding the first bonding layer to the second bonding layer.

Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: An acoustic metasurface structure is configured to absorb sounds. The acoustic metasurface structure comprises a main body, an externally-connecting configuration and an inner configuration. The externally-connecting configuration and the inner configuration are respectively formed inside the main body. An externally-connecting tube of the externally-connecting configuration is in fluid communication with an external environment and an externally-connecting cavity of the externally-connecting configuration. An inner tube of the inner configuration is in fluid communication with the externally-connecting cavity and an inner cavity of the inner configuration. With the externally-connecting configuration and the inner configuration forming a series-type structure in the main body, the acoustic metasurface structure increases an acoustic impedance.

Abstract: Throughput is preserved in a distributed system while maintaining concurrency by pushing a commit wait period to client commit paths and to future readers. As opposed to servers performing commit waits, the servers assign timestamps, which are used to ensure that causality is preserved. When a server executes a transaction that writes data to a distributed database, the server acquires a user-level lock, and assigns the transaction a timestamp equal to a current time plus an interval corresponding to bounds of uncertainty of clocks in the distributed system. After assigning the timestamp, the server releases the user-level lock. Any client devices, before performing a read of the written data, must wait until the assigned timestamp is in the past.

Abstract: An antenna module includes two antenna units, two isolation members, and a grounding member. Each antenna unit consists of two feeding ends, two first radiators, and two second radiators. The isolating members are disposed between the first and second portions of each antenna unit. The grounding member is disposed beside the two antenna units and the two isolation members. A first slot is formed among each first radiator, the second radiator, and the grounding member. The two second radiators are connected to the third radiator. A third slot is formed between the second radiator and the second portion. The two antenna units are symmetric to the fourth slot in a mirrored manner, and the two first portions have widths gradually changing along an extending direction of the fourth position.

Abstract: A semiconductor device includes: a substrate; a seed layer disposed on the substrate; a compound semiconductor stack layer disposed on the seed layer; and a source metal layer and a drain metal layer disposed on the compound semiconductor stack layer. The semiconductor device further includes a conductive layer at least partially covering the source metal layer and the drain metal layer, and covering opposing side surfaces of the seed layer and opposing side surfaces of the compound semiconductor stack layer. The conductive layer electrically connects the seed layer and the source metal layer.

Abstract: A multilayer polymer capacitor (MLPC), including a casing, a multilayer core, an electroplated positive terminal, a first electroplated negative terminal, and a second electroplated negative terminal. The casing includes a casing body and a cover plate. The casing body is provided with an accommodating cavity, whose bottom is provided with a through hole. The multilayer core is provided in the accommodating cavity. An anode lead-out part and a cathode lead-out part are provided at two ends of the accommodating cavity, respectively. The electroplated positive terminal and the first electroplated negative terminal are provided on outer side surfaces of two ends of the casing, respectively. The second electroplated negative terminal is provided on an outer bottom surface of the casing, and is electrically connected to the multilayer core.

Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.

Abstract: A dual-polarized patch antenna includes a radiator layer, at least one middle layer disposed below the radiator layer, a ground plane layer disposed below the middle layer to provide a reference potential, and a feed layer disposed below the ground plane layer. The radiator layer includes an insulation substrate that has a top surface and a bottom surface, a base patch that is disposed on the bottom surface, and a top patch that is disposed on the top surface, and that is spaced apart from the base patch by a patch distance. The top patch includes a center portion and an annular portion that encircles and is spaced apart from the center portion. The feed layer includes a feed substrate and two feed lines. The two feed lines are arranged substantially perpendicular to each other for feeding electrical signals.

Abstract: The disclosed technology is directed to a computing device for detecting and preventing melting of a component of the computing device. In some examples, the computing device includes a cable that connects a power supply unit and an add-on card, and a thermal protection controller. Based on a sensor signal from a temperature sensor of the cable, the thermal protection controller determines that a temperature associated with the cable exceeds a threshold temperature. Responsive to determining that the temperature associated with the cable exceeds the threshold temperature, the thermal protection controller causes the power supply unit to cease supplying power to the add-on card by transmitting an overtemperature signal through the cable.

Abstract: The present invention relates to a novel cyclic peptide carrier in the field of pharmaceutical technology and its various forms, where the cyclic peptide has the general sequence formula P-(X)m-Cys-(Y)n-Cys-(Z)o-P. The invention also encompasses the construction and preparation technology of a composition or formulation formed by the novel cyclic peptide carrier carrying nucleic acids, drugs, or therapeutic agents. Furthermore, it involves a method for effectively delivering nucleic acids to cells, tissues, or organisms using the composition or formulation, as well as its medical applications.

Abstract: An electronic device is provided that determines initial three-dimensional (3D) coordinates of a lighting device. The electronic device controls an emission of light from the lighting device based on control signals. The emitted light includes at least one of a pattern of alternating light pulses or a continuous light pulse. The electronic device controls a plurality of imaging devices to capture a first plurality of images that include information about the emitted light. Based on the determined initial 3D coordinates and the information about the emitted light included in the first plurality of images, the electronic device estimates a plurality of rotation values and a plurality of translation values of each imaging device. Based on the plurality of rotation values and the plurality of translation values, the electronic device applies a simultaneous localization and mapping process for each imaging device, for spatial synchronization of the plurality of imaging devices.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

Abstract: An embedded circuit board, made without gas bubbles or significant internal gaps according to a manufacturing method which is provided, includes an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces and a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.

Abstract: A cart for wafer transportation includes a cart body, a separator disposed between first and second wafer holders, an airtight lock configured to seal the cart body. A wafer transfer system includes a cart including a space for holding a wafer holder, a first workstation configured to load the wafer holder into the space and pressurize the space, and a second workstation configured to depressurize the space and unload the wafer holder from the space, wherein the cart is transportable between the first workstation and the second workstation. A method for transporting wafers includes docking a cart in a workstation; loading a wafer holder into a space of the cart; pressurizing the space to cause a pressure of the space to be greater than an atmospheric pressure; maintaining the pressure of the space at the pressure; and moving the cart carrying the wafer holder away from the workstation.

Abstract: The present invention relates to crystalline forms of a KRas G12C inhibitor and salt thereof. In particular, the present invention relates to crystalline forms of the KRas G12C inhibitor 2-[(2S)-4-[7-(8-chloro-1-naphthyl)-2-[[(2S)-1-methylpyrrolidin-2-yl]methoxy]-6,8-dihydro-5H-pyrido[3,4-d]pyrimidin-4-yl]-1-(2-fluoroprop-2-enoyl)piperazin-2-yl]acetonitrile, pharmaceutical compositions comprising the crystalline forms, processes for preparing the crystalline forms and methods of use thereof.

Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.