Abstract: In an embodiment, an apparatus comprising: a heater configured to heat a wafer located on a wafer staging area of the heater, the heater comprising a heater shaft extending below the wafer staging area; and a heater lift assembly comprising: a lift shaft configured to move the heater shaft in a vertical direction; a clamp that connects the heater shaft to the lift shaft; and a damper disposed on top of the clamp.

Abstract: A method for performing dynamic super-band operation (DSO) in a wireless communication system and associated apparatus are provided, where a plurality of non-access-point stations (non-AP STAs) are wirelessly linking to a first access point (AP) having a maximum clear channel assessment (CCA) bandwidth capability corresponding to a maximum CCA bandwidth, and the non-AP STAs are able to link to the first AP via a plurality of channels within the maximum CCA bandwidth, respectively. The method may include: providing a maximum transceiver bandwidth capability for at least one of the non-AP STAs smaller than the maximum CCA bandwidth capability of the first AP; and dynamically determining a first channel among the plurality of channels for data transmission of the first AP and the at least one of the non-AP STAs, based on channel utilization status of the plurality of channels within the maximum CCA bandwidth.

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

Abstract: Systems, apparatuses and methods may provide for a multi-deck non-volatile memory architecture with an improved wordline bus and bitline bus configuration. For example, wordline busses and bitline busses may be positioned so as to be located over the junctions between two tiles, e.g., between a memory tile and a termination tile and between two memory tiles. Additionally, multi-deck non-volatile memory architectures may utilize data shifting to select which one of a plurality of wordline drivers and a plurality of bitline drivers are in communication with a data circuit of each memory tile. In a configuration where wordline busses and bitline busses have been positioned so as to be located over the junctions between two tiles, such data shifting directions may be able to be implemented with a limited number of shifting direction.

Abstract: A ball detection device contains a support rack, a target plate, a sensing module, and a control unit. The support rack includes a fixing portion. The target plate includes nine marking zones, and a respective one marking zone has a passing orifice. The sensing module includes multiple ultrasonic sensors corresponding to the nine marking zones of the target plate, and a respective one ultrasonic sensor is received in the fixing portion and corresponds to the passing orifice, such that when the respective one ultrasonic sensor emits ultrasounds to the respective one marking zone, the ultrasounds emit out of the target plate via the passing orifice, thus sensing a ball hitting position and a ball pitching speed by using the respective one ultrasonic sensor. The control unit is electrically connected with the sensing module and is configured to record and display the ball hitting position and the ball pitching speed.

Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.

Abstract: A semiconductor device includes a substrate; an isolation structure over the substrate; a fin over the substrate and the isolation structure; a gate structure engaging a first portion of the fin; first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin; source/drain (S/D) features adjacent to the first sidewall spacers; and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride. The second sidewall spacers and the second portion of the fin include a same dopant, wherein the dopant includes phosphorus.

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

Abstract: Paxos transactions are pipelined in a distributed database formed by a plurality of replica servers. A leader server is selected by consensus of the replicas, and receives a lock on leadership for an epoch. The leader gets Paxos log numbers for the current epoch, which are greater than the numbers allocated in previous epochs. The leader receives database write requests, and assigns a Paxos number to each request. The leader constructs a proposed transaction for each request, which includes the assigned Paxos number and incorporates the request. The leader transmits the proposed transactions to the replicas. Two or more write requests that access distinct objects in the database can proceed simultaneously. The leader commits a proposed transaction to the database after receiving a plurality of confirmations for the proposed transaction from the replicas. After all the Paxos numbers have been assigned, inter-epoch tasks are performed before beginning a subsequent epoch.

Abstract: A hybrid power conversion circuit includes a high-side switch, a low-side switch, a transformer, a resonance tank, a first switch, a second switch, a first synchronous rectification switch, a second synchronous rectification switch, and a third switch. The resonance tank has an external inductor, an external capacitance, and an internal inductor. The first switch is connected to the external inductor. The second switch and a first capacitance form a series-connected path, and is connected to the external capacitance. The first and second synchronous rectification switches are respectively coupled to a first winding and a second winding. The third switch is connected to the second synchronous rectification switch. When an output voltage is less than a voltage interval, the hybrid power conversion circuit operates in a hybrid flyback conversion mode, and otherwise the hybrid power conversion circuit operates in a resonance conversion mode.

Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers.

Abstract: Throughput is preserved in a distributed system while maintaining concurrency by pushing a commit wait period to client commit paths and to future readers. As opposed to servers performing commit waits, the servers assign timestamps, which are used to ensure that causality is preserved. When a server executes a transaction that writes data to a distributed database, the server acquires a user-level lock, and assigns the transaction a timestamp equal to a current time plus an interval corresponding to bounds of uncertainty of clocks in the distributed system. After assigning the timestamp, the server releases the user-level lock. Any client devices, before performing a read of the written data, must wait until the assigned timestamp is in the past.

Abstract: A gas tube, a gas supply system containing the same and a semiconductor manufacturing method using the same are provided. The gas tube includes a porous material body and a resistant sheath surrounding the porous material body. The porous material body has a hollow tube structure and an empty cavity inside the hollow tube structure. The porous material body is hydrophobic and has a plurality of pores therein. The resistant sheath is disposed on the porous material body and surrounds the porous material body. The resistant sheath includes a plurality of holes penetrating through the resistant sheath.

Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

Abstract: A method of 3D motion reconstruction of outdoor, highly flexible moving subjects with multiple cameras on drones is described herein. A multi-drone capturing system is used to remove the restriction of a dedicated virtual reality shooting place, “the hot seat,” so that the actor/target is able to perform agile or long-distance activities outdoor. The subject's 3D pose parameters are estimated by the captured multi-view images by the drones, and the sequence of poses becomes the motion in time to control the animation of a pre-built 3D model. The method is able to be directly integrated into an existing Virtual Reality/Augmented reality (VR/AR) production chain, and the subject is able to be extended to animals that are difficult to be contained in a VR camera mesh space.

Abstract: The disclosure provides a power transmission system and method. The power transmission method includes: determining to perform a charging operation or a discharge operation between a battery module and a power supplying/receiving module according to a handshake procedure performed by a power transmission module. Performing the charging operation includes: adjusting a supply voltage outputted by the power supplying/receiving module; and converting the supply voltage into a charging voltage received by the battery module to charge the battery module. Performing the discharging operation includes: converting a discharge voltage outputted by the battery module into a required voltage required by the power supplying/receiving module to supply the power supplying/receiving module. The charging operation or the discharging operation is performed in a maximum power mode, an optimal efficiency mode or a combination thereof between the battery module and the power supplying/receiving module.

Abstract: The present disclosure provides a DC motor driving system including a DC motor, a power supply device, a switch circuit, and a microprocessor. The power supply device provides an input electrical energy. The switch circuit receives the input electrical energy and outputs a motor electrical energy, which includes a motor power and a motor voltage, to the DC motor. The DC motor driving system switchably works in a constant-voltage mode, a first variable-voltage mode, or a second variable-voltage mode. In the constant-voltage mode, the input electrical energy remains unchanged. In the first variable-voltage mode, the microprocessor controls the power supply device to adjust the input electrical energy for increasing the motor voltage and the motor power. In the second variable-voltage mode, the microprocessor controls the power supply device to adjust the input electrical energy for decreasing the motor voltage and keeping the motor power unchanged.

Abstract: The present invention provides an electronic device including a receiving circuit, a buffer, an output circuit and a control circuit. The receiving circuit is configured to receive input image data. The buffer is configured to temporarily store the input image data. The output circuit is configured to read the input image data from the buffer to generate output image data. The control circuit is configured to the generate a control signal according to a bit depth of the input image data, to dynamically control a delay time for the output circuit to generate the output image data.

Abstract: A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is checked, using machine learning, whether the at least one fail bit is unrepairable, according to the location of the at least one fail bit, and the available repair resource. When the checking indicates that the at least one fail bit is not unrepairable, it is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected.

Abstract: Some implementations described herein provide a semiconductor device and methods of formation. The semiconductor device includes a gate-all-around transistor having one or more dielectric regions that include or more dielectric gases. The dielectric regions may include a first dielectric region between epitaxial regions (e.g., source/drain regions) and a first portion of a gate structure of the gate-all-around transistor. The dielectric regions may further include a second dielectric region between a contact structure of gate-all-around transistor and a second portion of the gate structure. By including the dielectric regions in the gate-all-around transistor, a parasitic capacitance associated with the gate-all-around transistor may be reduced relative to another gate-all-around transistor not including the dielectric regions.