Patents by Inventor Cheng-Yuan Tsai

Cheng-Yuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    Publication number: 20210343849
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 4, 2021
    Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
  • RRAM device with improved performance
    Patent number: 11165021
    Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) device. In some embodiments, the method may be performed by forming a first electrode structure over a substrate. A doped data storage element is formed over the first electrode structure. The doped data storage element is formed by forming a first data storage layer over the first electrode structure and forming a second data storage layer over the first data storage layer. The first data storage layer is formed to have a first doping concentration of a dopant and the second data storage layer is formed to have a second doping concentration of the dopant that is less than the first doping concentration. A second electrode structure is formed over the doped data storage element.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Bi-Shen Lee
  • Film scheme for bumping
    Patent number: 11164836
    Abstract: A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Chang, Chern-Yow Hsu, Cheng-Yuan Tsai, Kong-Beng Thei
  • RESISTIVE MEMORY CELL WITH SWITCHING LAYER COMPRISING ONE OR MORE DOPANTS
    Publication number: 20210336135
    Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure disposed between a top electrode and a bottom electrode. The data storage structure includes a lower switching layer overlying the bottom electrode, and an upper switching layer overlying the lower switching layer. The lower switching layer comprises a dielectric material doped with a first dopant.
    Type: Application
    Filed: July 27, 2020
    Publication date: October 28, 2021
    Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee
  • Trim wall protection method for multi-wafer stacking
    Patent number: 11152276
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Kuo-Ming Wu
  • Bonding support structure (and related process) for wafer stacking
    Patent number: 11139210
    Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Chih-Hui Huang, Kuo-Ming Wu
  • CAPACITOR STRUCTURE AND METHOD OF MAKING THE SAME
    Publication number: 20210305357
    Abstract: A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: Jian-Shiou HUANG, Chia-Shiung TSAI, Cheng-Yuan TSAI, Hsing-Lien LIN, Yao-Wen CHANG
  • Techniques for wafer stack processing
    Patent number: 11127635
    Abstract: The present disclosure relates to a method for forming a multi-dimensional integrated chip structure. In some embodiments, the method may be performed by bonding a second substrate to an upper surface of a first substrate. A first edge trimming cut is performed along a first loop and extends into a first peripheral portion of the second substrate. A second edge trimming cut is performed along a second loop and extends into a second peripheral portion of the second substrate and into the first substrate. A third edge trimming cut is performed along a third loop and extends into a third peripheral portion of the first substrate.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Lung Lin, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Hau-Yi Hsiao
  • MIM capacitor and method of forming the same
    Patent number: 11121208
    Abstract: A capacitive device includes: a first metal plate; a first planar dielectric layer disposed on the first metal plate; a second planar dielectric layer disposed on the first planar dielectric layer; a third planar dielectric layer disposed on the second planar dielectric layer; and a second metal plate disposed on the third planar dielectric layer; wherein the first planar dielectric layer has a first dielectric constant, the second planar dielectric layer has a second dielectric constant, and the third planar dielectric layer has a third dielectric constant, and the second dielectric constant is different from the first dielectric constant and the third dielectric constant, the second planar dielectric layer includes Tantalum pentoxide.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsing-Lien Lin, Hai-Dang Trinh, Cheng-Yuan Tsai
  • DIFFUSION BARRIER LAYER IN PROGRAMMABLE METALLIZATION CELL
    Publication number: 20210280780
    Abstract: Some embodiments relate to a memory device. The memory device includes a bottom electrode overlying a substrate. A data storage layer overlies the bottom electrode. A top electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the bottom electrode to the top electrode. A diffusion barrier layer is disposed between the data storage layer and the top electrode.
    Type: Application
    Filed: March 3, 2020
    Publication date: September 9, 2021
    Inventors: Albert Zhong, Cheng-Yuan Tsai, Hai-Dang Trinh, Shing-Chyang Pan
  • Semiconductor structure with ultra thick metal and manufacturing method thereof
    Patent number: 11114378
    Abstract: The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Fa Lu, Cheng-Yuan Tsai, Ching-Chung Hsu, Chung-Long Chang
  • MEMORY DEVICE STRUCTURE
    Publication number: 20210273161
    Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate and a data storage element over the semiconductor substrate. The structure also includes an ion diffusion barrier element over the data storage element and a protective element extending along a sidewall of the ion diffusion barrier element. A bottom surface of the protective element is between a top surface of the data storage element and a bottom surface of the data storage element. The structure further includes a first electrode electrically connected to the data storage element and a second electrode electrically connected to the data storage element.
    Type: Application
    Filed: May 19, 2021
    Publication date: September 2, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hai-Dang TRINH, Hsing-Lien LIN, Cheng-Yuan TSAI
  • SURFACE TREATMENT AND PASSIVATION FOR HIGH ELECTRON MOBILITY TRANSISTORS
    Publication number: 20210265486
    Abstract: A semiconductor device includes a compound semiconductor layer comprising a III-V material; a first layer on the compound semiconductor layer and comprising oxygen, nitrogen, and a material included in the compound semiconductor layer; a second layer over the first layer, wherein at least a portion of the second layer comprises a single crystalline structure or a polycrystalline structure; a dielectric layer over the second layer; and a source/drain electrode extending through the dielectric layer, the second layer, and the first layer and into the compound semiconductor layer.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Inventors: Han-Chin Chiu, Cheng-Yuan Tsai
  • Image sensor having stacked conformal films
    Patent number: 11101307
    Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yu Lai, Min-Ying Tsai, Yeur-Luen Tu, Hai-Dang Trinh, Cheng-Yuan Tsai
  • SEMICONDUCTOR STRUCTURE HAVING INTEGRATED INDUCTOR THEREIN
    Publication number: 20210242303
    Abstract: A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer, wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.
    Type: Application
    Filed: April 22, 2021
    Publication date: August 5, 2021
    Inventors: MING-CHE LEE, SHENG-CHAU CHEN, I-NAN CHEN, CHENG-HSIEN CHOU, CHENG-YUAN TSAI
  • IMAGE SENSOR SCHEME FOR OPTICAL AND ELECTRICAL IMPROVEMENT
    Publication number: 20210225919
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a photodetector arranged within a substrate. The substrate has surfaces defining one or more protrusions arranged along a first side of the substrate over the photodetector. One or more isolation structures are arranged within one or more trenches defined by sidewalls of the substrate arranged on opposing sides of the photodetector. The one or more trenches extend from the first side of the substrate to within the substrate. The one or more isolation structures respectively include a reflective medium configured to reflect electromagnetic radiation.
    Type: Application
    Filed: April 1, 2021
    Publication date: July 22, 2021
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Keng-Yu Chou, Yeur-Luen Tu
  • Semiconductor device and fabrication method thereof
    Patent number: 11069785
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20210202809
    Abstract: A semiconductor structure is provided. The semiconductor structure includes metallization structure, a plurality of conductive pads, and a dielectric layer. The plurality of conductive pads is over the metallization structure. The dielectric layer is on the metallization structure and covers the conductive pad. The dielectric layer includes a first dielectric film, a second dielectric film, and a third dielectric film. The first dielectric film is on the conductive pad. The second dielectric film is on the first dielectric film. The third dielectric film is on the second dielectric film. The a refractive index of the first dielectric film is smaller than a refractive index of the second dielectric film, and the refractive index of the second dielectric film is smaller than a refractive index of the third dielectric film.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Inventors: CHIA-HUA LIN, YAO-WEN CHANG, CHII-MING WU, CHENG-YUAN TSAI, EUGENE I-CHUN CHEN, TZU-CHUNG TSAI
  • Gas shower head with plural hole patterns and with corresponding different plural hole densities and film formation method
    Patent number: 11041242
    Abstract: A gas shower head includes a plate, a plurality of central holes disposed in a central region of the plate, and a plurality of peripheral holes disposed in a peripheral region of the plate. The central holes are configured to form a first portion of a material film, and the peripheral holes are configured to form a second portion of the material film. A hole density in the peripheral region is greater than a hole density in the central region. The first portion of the material film includes a first thickness corresponding to the hole density in central region, and the second portion of the material film includes a second thickness corresponding to the hole density in peripheral region and greater than the first thickness.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Hui Huang, Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Capacitor structure and method of making the same
    Patent number: 11038010
    Abstract: A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Jian-Shiou Huang, Chia-Shiung Tsai, Cheng-Yuan Tsai, Hsing-Lien Lin, Yao-Wen Chang