Patents by Inventor Cheng-Yuan Tsai

Cheng-Yuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230129760
    Abstract: A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.
    Type: Application
    Filed: December 23, 2022
    Publication date: April 27, 2023
    Inventors: Kuo-Ming WU, Ming-Che LEE, Hau-Yi HSIAO, Cheng-Hsien CHOU, Sheng-Chau CHEN, Cheng-Yuan TSAI
  • Patent number: 11637239
    Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode over a substrate. A data storage layer is over the bottom electrode and has a first thickness. A capping layer is over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 1.9 and approximately 3 times thicker than the first thickness. A top electrode is over the capping layer.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chin-Chieh Yang, Yu-Wen Liao, Wen-Ting Chu, Chia-Shiung Tsai
  • Publication number: 20230123774
    Abstract: Various embodiments of the present disclosure are directed towards an amorphous bottom electrode structure (BES) for a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode, an insulator layer overlying the bottom electrode, and a top electrode overlying the insulator layer. The bottom electrode comprises a crystalline BES and the amorphous BES, and the amorphous BES overlies the crystalline BES and forms a top surface of the bottom electrode. Because the amorphous BES is amorphous, instead of crystalline, a top surface of the amorphous BES may have a small roughness compared to that of the crystalline BES. Because the amorphous BES forms the top surface of the bottom electrode, the top surface of the bottom electrode may have a small roughness compared to what it would otherwise have if the crystalline BES formed the top surface. The small roughness may improve a lifespan of the MIM capacitor.
    Type: Application
    Filed: January 12, 2022
    Publication date: April 20, 2023
    Inventors: Hsing-Lien Lin, Jui-Lin Chu, Cheng-Yuan Tsai
  • Publication number: 20230103309
    Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a conductive structure over a semiconductor substrate. A first dielectric layer is over the conductive structure. A second dielectric layer is over the first dielectric layer. An interconnect structure is over the conductive structure and disposed in the first and second dielectric layers. The interconnect structure has a protrusion in direct contact with a sidewall of the conductive structure. The interconnect structure comprises an interconnect liner surrounding a conductive interconnect body.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 6, 2023
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang
  • Publication number: 20230101989
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having a first horizontally extending surface and a second horizontally extending surface above the first horizontally extending surface as viewed in a cross-sectional view. The first horizontally extending surface continuously wraps around an outermost perimeter of the second horizontally extending surface in a closed loop as viewed in a plan-view. A second substrate is disposed over the first substrate and includes a third horizontally extending surface above the second horizontally extending surface as viewed in the cross-sectional view. The second horizontally extending surface continuously wraps around an outermost perimeter of the third horizontally extending surface in a closed loop as viewed in the plan-view.
    Type: Application
    Filed: December 7, 2022
    Publication date: March 30, 2023
    Inventors: Yung-Lung Lin, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Hau-Yi Hsiao
  • Publication number: 20230100181
    Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.
    Type: Application
    Filed: December 7, 2022
    Publication date: March 30, 2023
    Inventors: Fa-Shen Jiang, Hsia-Wei Chen, Hsun-Chung Kuang, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Patent number: 11610812
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
  • Publication number: 20230067249
    Abstract: Provided are an integrated circuit (IC) and a method of forming the same. The IC includes a substrate; a conductive layer, disposed on the substrate; a barrier layer, disposed on the conductive layer; an etching stop layer, covering a sidewall of the barrier layer and extending on a first portion of a top surface of the barrier layer; and at least one capacitor structure, disposed on a second portion of the top surface of the barrier layer.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Lee, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Publication number: 20230069081
    Abstract: A thin-film deposition system includes a top plate positioned above a wafer and configured to generate a plasma during a thin-film deposition process. The system includes a gap sensor configured to generate sensor signals indicative of a gap between the wafer and the top plate. The system includes a control system configured to adjust the gap during the thin-film deposition process responsive to the sensor signals.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Sheng-Chan LI, Sheng-Chau CHEN, Cheng-Hsien CHOU, Cheng-Yuan TSAI
  • Publication number: 20230062974
    Abstract: In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defining a processing chamber. Within the processing chamber is a wafer chuck configured to hold a substrate. Further, a bell jar structure is arranged over the wafer chuck such that an opening of the bell jar structure faces the wafer chuck. A plasma coil is arranged over the bell jar structure. An oxygen source coupled to the processing chamber and configured to input oxygen gas into the processing chamber.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Yen-Liang Lin, Chia-Wen Zhong, Yao-Wen Chang, Min-Chang Ching, Kuo Liang Lu, Cheng-Yuan Tsai, Ru-Liang Lee
  • Patent number: 11594678
    Abstract: Some embodiments relate to a memory device. The memory device includes a bottom electrode overlying a substrate. A data storage layer overlies the bottom electrode. A top electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the bottom electrode to the top electrode. A diffusion barrier layer is disposed between the data storage layer and the top electrode.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: February 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Zhong, Cheng-Yuan Tsai, Hai-Dang Trinh, Shing-Chyang Pan
  • Patent number: 11581254
    Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Paul Yang, Tsun-Kai Tsao, Sheng-Chau Chen, Sheng-Chan Li, Cheng-Yuan Tsai
  • Patent number: 11575021
    Abstract: A semiconductor device includes a compound semiconductor layer comprising a III-V material; a first layer on the compound semiconductor layer and comprising oxygen, nitrogen, and a material included in the compound semiconductor layer; a second layer over the first layer, wherein at least a portion of the second layer comprises a single crystalline structure or a polycrystalline structure; a dielectric layer over the second layer; and a source/drain electrode extending through the dielectric layer, the second layer, and the first layer and into the compound semiconductor layer.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Chin Chiu, Cheng-Yuan Tsai
  • Patent number: 11552066
    Abstract: A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Ming Wu, Ming-Che Lee, Hau-Yi Hsiao, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Patent number: 11545202
    Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fa-Shen Jiang, Hsia-Wei Chen, Hsun-Chung Kuang, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Patent number: 11545395
    Abstract: The present disclosure, in some embodiments, relates to a multi-dimensional integrated chip structure. The multi-dimensional integrated chip structure includes a first substrate having a first upper surface and a second upper surface above the first upper surface. A first outermost perimeter of the first upper surface is larger than a second outermost perimeter of the second upper surface. A second substrate is over the first substrate. The second substrate has a third upper surface above the second upper surface. A third outermost perimeter of the third upper surface is smaller than the second outermost perimeter of the second upper surface.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Lung Lin, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Hau-Yi Hsiao
  • Publication number: 20220392906
    Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 8, 2022
    Inventors: Bi-Shen Lee, Yi Yang Wei, Hsing-Lien Lin, Hsun-Chung Kuang, Cheng-Yuan Tsai, Hai-Dang Trinh
  • Publication number: 20220393101
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a memory cell with a sidewall spacer, and/or an etch stop layer, doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field produced by the electric dipole, thereby reducing the effect of the electric field on the memory cell.
    Type: Application
    Filed: July 29, 2021
    Publication date: December 8, 2022
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Patent number: 11522066
    Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • Publication number: 20220375789
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Application
    Filed: August 4, 2022
    Publication date: November 24, 2022
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li