Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.

Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

Abstract: A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.

Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

Abstract: A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.

Abstract: A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

Abstract: A method including providing a silicon-on-insulator (SOI) substrate including a SOI layer, a buried oxide layer, and a base layer; the buried oxide layer is located below the SOI layer and above the base layer, and the buried oxide layer insulates the SOI layer from the base layer; etching a deep trench into the SOI substrate, the deep trench having a sidewall and a bottom, the deep trench extends from a top surface of the SOI layer, through the buried oxide layer, down to a location within the base layer; forming a dielectric liner on the sidewall and the bottom of the deep trench; forming a conductive fill material on top of the dielectric liner and substantially filling the deep trench, the fill material being thermally conductive; and transferring heat from the SOI layer to the base layer via the fill material.

Abstract: Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed.

Abstract: A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.

Abstract: A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.

Abstract: A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.

Abstract: In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

Abstract: A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.

Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

Abstract: Embodiments of the invention relate generally to semiconductor devices and, more particularly, to semiconductor devices having field effect transistors (FETs) with a low body resistance and, in some embodiments, a self-balanced body potential where multiple transistors share same body potential. In one embodiment, the invention includes a field effect transistor (FET) comprising a source within a substrate, a drain within the substrate, and an active gate atop the substrate and between the source and the drain, an inactive gate structure atop the substrate and adjacent the source or the drain, a body adjacent the inactive gate, and a discharge path within the substrate for releasing a charge from the FET, the discharge path lying between the active gate of the FET and the body, wherein the discharge path is substantially perpendicular to a width of the active gate.

Abstract: After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor.

Abstract: A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.

Abstract: Methods of forming an electrically programmable fuse (e-fuse) structure and the e-fuse structure are disclosed. Various embodiments of forming the e-fuse structure include: forming a dummy poly gate structure to contact a surface of a silicon structure, the dummy poly gate structure extending only a part of a length of the silicon structure; and converting an unobstructed portion of the surface of the silicon structure to silicide to form a thinned strip of the silicide between two end regions.

Abstract: A method of fabricating a material having nanoscale pores is provided. In one embodiment, the method of fabricating a material having nanoscale pores may include providing a single crystal semiconductor. The single crystal semiconductor layer is then patterned to provide an array of exposed portions of the single crystal semiconductor layer having a width that is equal to the minimum lithographic dimension. The array of exposed portion of the single crystal semiconductor layer is then etched using an etch chemistry having a selectivity for a first crystal plane to a second crystal plane of 100% or greater. The etch process forms single or an array of trapezoid shaped pores, each of the trapezoid shaped pores having a base that with a second width that is less than the minimum lithographic dimension.