Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.

Abstract: Disclosed is a folding cutting mat. As its main features, the folding cutting mat includes more than one 4-piece folding unit, the single 4-piece folding unit includes a folding face and a flipping face integrally formed, wherein the folding face includes left and right side faces and a first folding line to connect the left and right side faces, the flipping face includes left and right side plates and a separating gap to separate the left and right side plates; the left side face and left side plate are connected through a second folding line, the right side face and the right side plate are connected through a third folding line. With the size of the folded 4-piece folding unit reduced to one fourth of the size in the unfolded state, the size of the folded cutting mat is considerably reduced to facilitate transportation and storage.

Abstract: A reinforced folding cutting mat including a mat, which is a plate body thicker than 0.5 mm. The mat is formed with at least a cutting face made of cutting resistant plastic material. At least a fold tangent is formed in at least one part of mat, so that the mat can be bent using the fold tangent as fold line, and the one fold tangent includes a plurality of deep cutting edges and a plurality of reinforcing ribs with different cutting depths. The reinforcing ribs are adjacent to the deep cutting edges. The folding cutting mat is a product a one-piece product that is reinforced and has a more durable fold tangent form.

Abstract: The present invention discloses a bone void filler and a method for manufacturing the same by natural calcium-containing waste, which comprises steps of mixing 5-20 wt % of a calcium-containing waste powder, 5-20 wt % of acetic acid and a remaining weight percentage of water uniformly to obtain a mixing solution; adding 5-20 vol % of a diammonium hydrogen phosphate solution to the mixing solution to obtain a suspension; controlling a pH value of the suspension to obtain an alkaline solution; leaving the alkaline solution at room temperature for precipitation for 0.1 to 72 hours, centrifuging or suction filtrating the alkaline solution to obtain a precipitate, drying and grinding the precipitate to obtain hydroxyapatite; and mixing 30-60 wt % of a pore former and 30-60 wt % of the hydroxyapatite and a remaining weight percentage of a binder uniformly to form a mixture, compression molding the mixture in a mold and sintering the compression-molded mixture.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.

Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.

Abstract: A display device includes a first luminescent device, a second luminescent device, a multi-color strobe decoder, a pseudo signal circuit and a single-color driving circuit. The multi-color strobe decoder is configured to generate two gate control signals. The second luminescent device and the pseudo signal circuit are coupled to the multi-color strobe decoder. The single-color driving circuit is coupled to the first luminescent device and the multi-color strobe decoder. When the single-color driving circuit provides first current for driving the first luminescent device according to the first gate control signal and/or a brightness enhancing signal, the pseudo signal circuit is configured to couple a first bias voltage to the multi-color strobe decoder according to the first gate control signal. When the second gate control signal drives the second luminescent device, the second luminescent device is configure to couple a second bias voltage to the multi-color strobe decoder.

Abstract: A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: A lockable rotary cutting mat includes a base plate and a rotary plate. The central bottom portion of the rotary plate is assembled on the center of the base plate through a rotary connector. The rotary plate includes a cutting surface and a periphery. The periphery is formed with concave edge portions, and a locking component is provided at the corresponding position between the base plate and the rotary plate periphery. The locking component includes a moving base, a controller and a locking edge portion. The controller can be pushed along a movement guiding axis on the moving base. The locking edge portion is connected to, and can be driven by the controller to have locked and released positions. When the locking edge portion is at the locked position, it is aligned to, and is engaged with the corresponding concave edge portion, so that the rotary plate is fixed.

Abstract: A method of manufacturing a casing of an electronic device including the following steps is provided. A metallic housing is provided, wherein the metallic housing has an inner surface and an outer surface opposite to the inner surface and includes a back region and at least one side region. At least one gap, a plurality of apertures and a non-conductive layer are formed on the inner surface of the metallic housing, wherein the apertures is formed on a surface of the at least one gap, part of the non-conductive layer is formed in the at least one gap and extended from the back region to the at least one side region, and part of the non-conductive layer is extended into the apertures. Part of the metallic housing is removed for exposing part of the non-conductive layer, thereby forming a plurality of non-conductive spacers located in the at least one gap.

Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.

Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.

Abstract: A metallic housing of an electronic device including an inner surface, an outer surface and a first non-conductive spacer is provided. The outer surface is opposite to the inner surface, and the outer surface has a back side and lateral sides connecting with the back side. The inner surface is substantially a recessed structure. The metallic housing having a first gap and a second gap substantially located at two opposite ends of the metallic housing and being parallel with each other. The first gap and the second gap each communicates the inner surface and the outer surface. The first non-conductive spacer is disposed the first gap of the metallic housing.

Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.

Abstract: A multi-gate ferroelectric memory comprises a fin-shaped channel layer, a front ferroelectric layer disposed on one side of the fin-shaped channel layer, a back ferroelectric layer disposed on another side of the fin-shaped channel layer, a front gate attached to the front ferroelectric layer and away from the fin-shaped channel layer, wherein the front gate is configured to connect a word line, and a back gate attached to the back ferroelectric layer and away from the fin-shaped channel layer, wherein the back gate is configured to connect a bit line. The present disclosure further discloses a memory array device, comprises a plurality of the multi-gate ferroelectric memories arranged as an array, a plurality of word lines and a plurality of bit lines.

Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.