Patents by Inventor Chi-An JEN

Chi-An JEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11076466
    Abstract: A light intensity adjustment circuit includes a delay circuit, a switching circuit and a light-emitting circuit. The delay circuit includes a capacitor and is used to receive a first pulse width modulation signal and generate a delay signal according to the first pulse width modulation signal. The switching circuit includes a switching unit and an isolation circuit. The switching unit includes a control terminal coupled to the delay circuit and used to receive the delay signal, and a first terminal used to generate a current according to the delay signal. The isolation circuit is coupled to the first terminal of the switching unit and generate a second pulse width modulation signal according to the current. The light-emitting circuit is used to receive the second pulse width modulation signal and emit light accordingly.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: July 27, 2021
    Assignee: Qisda Corporation
    Inventors: Tsung-Hsun Wu, Chi-Jen Chen, Yuan-Ting Fang
  • Publication number: 20210204378
    Abstract: A light intensity adjustment circuit includes a delay circuit, a switching circuit and a light-emitting circuit. The delay circuit includes a capacitor and is used to receive a first pulse width modulation signal and generate a delay signal according to the first pulse width modulation signal. The switching circuit includes a switching unit and an isolation circuit. The switching unit includes a control terminal coupled to the delay circuit and used to receive the delay signal, and a first terminal used to generate a current according to the delay signal. The isolation circuit is coupled to the first terminal of the switching unit and generate a second pulse width modulation signal according to the current. The light-emitting circuit is used to receive the second pulse width modulation signal and emit light accordingly.
    Type: Application
    Filed: September 24, 2020
    Publication date: July 1, 2021
    Inventors: Tsung-Hsun Wu, Chi-Jen Chen, Yuan-Ting Fang
  • Patent number: 11044435
    Abstract: A driver circuit includes a first voltage conversion unit, a second voltage conversion unit, a third voltage conversion unit, a light driver and a control circuit. The first voltage conversion unit may convert a first voltage to a second voltage. The second voltage conversion unit may convert the second voltage to a third voltage in a non-electrically isolated manner. The third voltage conversion unit may convert the second voltage to a fourth voltage in a non-electrically isolated manner. The light driver may receive the third voltage and a control signal to generate a control current according to the control signal. The control circuit may receive the fourth voltage and an image signal to generate the control signal according to the image signal.
    Type: Grant
    Filed: June 2, 2019
    Date of Patent: June 22, 2021
    Assignee: Qisda Corporation
    Inventors: Fang-Chieh Lu, Chi-Jen Chen, Chuan-Chu Chen, Ching-Ying Tsou
  • Publication number: 20210183688
    Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.
    Type: Application
    Filed: February 26, 2021
    Publication date: June 17, 2021
    Inventors: Chia Hsuan Lee, Chun-Wei Hsu, Chia-Wei Ho, Chi-Hsiang Shen, Li-Chieh Wu, Jian-Ci Lin, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, Liang-Guang Chen, Kuo-Hsiu Wei, Kei-Wei Chen
  • Patent number: 11037799
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yi-Sheng Lin, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, Te-Ming Kung, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Chun-Wei Hsu, Yang-Chun Cheng
  • Publication number: 20210163859
    Abstract: A semiconductor cleaning solution for cleaning a surface of a semiconductor device, and a method of use and a method of manufacture of the cleaning solution are disclosed. In an embodiment, a material is polished away from a first surface of the semiconductor device and the first surface is cleaned with the cleaning solution. The cleaning solution may include a host having at least one ring. The host may have a hydrophilic exterior and a hydrophobic interior.
    Type: Application
    Filed: February 10, 2021
    Publication date: June 3, 2021
    Inventors: Pinlei Edmund Chu, Chun-Wei Hsu, Ling-Fu Nieh, Chi-Jen Liu, Liang-Guang Chen, Yi-Sheng Lin
  • Publication number: 20210129587
    Abstract: A non-pneumatic tire includes a tread layer and a spoke layer including an inner cylinder and several spoke assemblies. The tread layer is annular and has a maximum outer diameter of the non-pneumatic tire and is adapted to be in contact with a ground. The spoke assemblies extend in a radial direction of the non-pneumatic tire and are arranged around an axial core of the non-pneumatic tire. An end of each spoke assembly is connected to the inner cylinder, and another end thereof is connected to the tread layer. Each spoke assembly includes a straight spoke, a bending spoke, and a connecting rib. Each bending spoke includes a first segment and a second segment, which are not connected in a straight line. Each connecting rib has a first end connected to the straight spoke and a second end opposite to the first end and connected to the bending spoke. When the non-pneumatic tire bears a weight and is squeezed, the spoke assemblies do not get in contact with one another.
    Type: Application
    Filed: August 20, 2020
    Publication date: May 6, 2021
    Applicant: KENDA RUBBER IND. CO., LTD.
    Inventors: CHI-JEN YANG, MIN-FAN HUANG, JIA-YI JIANG
  • Patent number: 10990125
    Abstract: A computer is provided, including a keyboard, a rotating plate, a pivot shaft and a screen. The rotating plate is movably disposed on the keyboard. The pivot shaft is connected to the rotating plate, and is movable relative to the keyboard. The screen is connected to the pivot shaft to move relative to the rotating plate.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 27, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Wen-Hung Tsai, Gwo-Chyuan Chen, Chi-Jen Yu, I-Chi Chen
  • Publication number: 20210111027
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
  • Patent number: 10976779
    Abstract: A computer is provided, including a keyboard, a pivot shaft, a supporting plate and a screen. The pivot shaft is movably disposed on the keyboard. The supporting plate is connected to the pivot shaft, and is rotatable relative to the keyboard, and includes a supporting plate pivot. The screen is connected to the supporting plate pivot to rotate relative to the supporting plate.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: April 13, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Wen-Hung Tsai, Gwo-Chyuan Chen, Chi-Jen Yu, I-Chi Chen, Po-Sheng Huang
  • Patent number: 10961487
    Abstract: A semiconductor cleaning solution for cleaning a surface of a semiconductor device, and a method of use and a method of manufacture of the cleaning solution are disclosed. In an embodiment, a material is polished away from a first surface of the semiconductor device and the first surface is cleaned with the cleaning solution. The cleaning solution may include a host having at least one ring. The host may have a hydrophilic exterior and a hydrophobic interior.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pinlei Edmund Chu, Chun-Wei Hsu, Ling-Fu Nieh, Chi-Jen Liu, Liang-Guang Chen, Yi-Sheng Lin
  • Publication number: 20210086344
    Abstract: A sewing tape measure with a print-on anti-slip structure includes a transparent substrate and a reference line unit disposed on top surface or a bottom surface of the transparent substrate. The reference line unit includes a plurality of lateral main reference lines and longitudinal main reference lines. Each adjacent longitudinal main reference line is provided with a plurality of secondary reference lines, and a no reference line area is defined between adjacent lateral main reference lines, adjacent longitudinal main reference lines and adjacent secondary reference lines. The plural print-on anti-slip parts are disposed on the bottom surface of the transparent substrate at the interval, each print-on anti-slip part is printed by the printing ink with a anti-slip property, and each print-on anti-slip part is distributed within the range of no reference line area.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventor: Chi-Jen CHEN
  • Publication number: 20210078129
    Abstract: A chemical mechanical polishing (CMP) system includes a polishing pad configured to polish a substrate. The CMP system further includes a heating system configured to adjust a temperature of the polishing pad. The heating system comprises at least one heating element spaced apart from the polishing pad. The CMP system further includes a sensor configured to measure the temperature of the polishing pad.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Yi-Sheng LIN, Chi-Hsiang SHEN, Chi-Jen LIU, Chun-Wei Hsu, Yang-Chun CHENG, Kei-Wei CHEN
  • Publication number: 20210082688
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.
    Type: Application
    Filed: November 10, 2020
    Publication date: March 18, 2021
    Inventors: Shich-Chang Suen, Li-Chieh Wu, Chi-Jen Liu, He Hui Peng, Liang-Guang Chen, Yung-Chung Chen
  • Publication number: 20210082837
    Abstract: An electronic package is provided and includes a plurality of electronic elements, a spacing structure connecting each of the plurality of electronic elements, and a plurality of conductive elements electrically connected to the plurality of electronic elements and serving as external contacts. The spacing structure has a recess to enhance the flexibility of the electronic elements after the electronic elements are connected to one another, thereby preventing the problem of warpage. A method for fabricating the electronic package is also provided.
    Type: Application
    Filed: May 6, 2020
    Publication date: March 18, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Yuan-Hung Hsu, Chi-Jen Chen
  • Patent number: 10952341
    Abstract: A casing of an electronic device including a metallic housing, a first non-conductive spacer and a second non-conductive spacer is provided. The metallic housing has an inner surface and an outer surface opposite to the inner surface, and the outer surface has a back side and lateral sides connecting with the back side. The inner surface is substantially a recessed structure. The metallic housing having a first gap and a second gap substantially located at two opposite ends of the metallic housing and being parallel with each other. The first non-conductive spacer is disposed the first gap, and the second non-conductive spacer is disposed in the second gap.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: March 16, 2021
    Assignee: HTC Corporation
    Inventors: Tim Chung-Ting Wu, Cheng-Chieh Chuang, Chi-Jen Lu, Chun-Lung Chu, Chien-Hung Lin
  • Publication number: 20210076522
    Abstract: A metallic housing of an electronic device including an inner surface, an outer surface and a first non-conductive spacer is provided. The outer surface is opposite to the inner surface, and the outer surface has a back side and lateral sides connecting with the back side. The inner surface is substantially a recessed structure. The metallic housing having a first gap and a second gap substantially located at two opposite ends of the metallic housing and being parallel with each other. The first gap and the second gap each communicates the inner surface and the outer surface. The first non-conductive spacer is disposed the first gap of the metallic housing.
    Type: Application
    Filed: November 17, 2020
    Publication date: March 11, 2021
    Applicant: HTC Corporation
    Inventors: Tim Chung-Ting Wu, Cheng-Chieh Chuang, Chi-Jen Lu, Chun-Lung Chu, Chien-Hung Lin
  • Publication number: 20210074603
    Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.
    Type: Application
    Filed: January 6, 2020
    Publication date: March 11, 2021
    Inventors: Hong-Da Chang, Chun-Chang Ting, Chi-Jen Chen
  • Patent number: 10937691
    Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia Hsuan Lee, Chun-Wei Hsu, Chia-Wei Ho, Chi-Hsiang Shen, Li-Chieh Wu, Jian-Ci Lin, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, Liang-Guang Chen, Kuo-Hsiu Wei, Kei-Wei Chen
  • Patent number: D910009
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: February 9, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chien-Ming Wu, Gwo-Chyuan Chen, Chi-Jen Yu