Patents by Inventor Chi-An JEN

Chi-An JEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11393983
    Abstract: The present disclosure provides phenyl biphenylpyrimidine compounds of formula (I) and an organic electroluminescent device using the same: wherein X1 and A1 each independently represents substituted or unsubstituted C6-30 aryl or substituted or unsubstituted C5-30 heteroaryl having at least one heteroatom selected from the group consisting of N, O, and S, and n represents an integer of 1 or 2.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: July 19, 2022
    Assignee: E-RAY OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Heh-Lung Huang, Teng-Chih Chao, Po-Wei Hsu, Yi-Huan Fu, Chi-Jen Lin
  • Publication number: 20220181225
    Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.
    Type: Application
    Filed: January 28, 2021
    Publication date: June 9, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
  • Publication number: 20220173052
    Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.
    Type: Application
    Filed: January 28, 2021
    Publication date: June 2, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsun Hsu, Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Rui-Feng Tai, Don-Son Jiang
  • Patent number: 11258995
    Abstract: A projector and a drive circuit thereof are provided. The projector includes a light source and a drive circuit. The light source includes at least one red light diode, at least one green light diode, at least one first blue light diode and at least one second blue light diode. The drive circuit includes a red light drive circuit, a green light drive circuit, a first blue light drive circuit and a second blue light drive circuit. The green light drive circuit outputs a green light drive signal to the green light diode according to a green light control signal. The second blue light drive circuit outputs a second blue light drive signal to the second blue light diode according to a second blue light control signal. The second blue light control signal and the green light drive signal have synchronous pulse.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: February 22, 2022
    Assignee: Qisda Corporation
    Inventors: Chi-Jen Chen, Fang-Chieh Lu, Chun-Hsiao Lin
  • Publication number: 20220017780
    Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one cationic surfactant having at least one nitrogen atom in the molecule. The slurry includes at least one liquid carrier, at least one abrasive and at least one pH adjusting agent, and has a pH of less than 7.0. The polishing method includes using the slurry composition with the cationic surfactant to polish a conductive layer. The integrated circuit comprises a block layer comprising the cationic surfactant between a sidewall of the conductive plug and an interlayer dielectric layer.
    Type: Application
    Filed: November 24, 2020
    Publication date: January 20, 2022
    Inventors: JI CUI, CHI-JEN LIU, CHIH-CHIEH CHANG, KAO-FENG LIAO, PENG-CHUNG JANGJIAN, CHUN-WEI HSU, TING-HSUN CHANG, LIANG-GUANG CHEN, KEI-WEI CHEN, HUI-CHI HUANG
  • Patent number: 11220770
    Abstract: A portable patchwork sewing tool kit includes: a base plate, the inner face thereof is provided with a first page and a second page which can be folded or unfolded optionally; a rotary cutting mat fixed to the first page, the rotary cutting mat comprises a bottom plate and a cutting plate pad screwed on the bottom plate through a pivot joint base to be rotated under stress; a detachable ironing mat fixed to the second page, including a core board, a cotton spreading layer covering the core board and a cotton fabric surface layer covering the cotton spreading layer, an ironing face formed outside the cotton fabric surface layer; and a plurality of pushing edges formed around the cutting plate pad and spaced apart.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: January 11, 2022
    Inventor: Chi-Jen Chen
  • Patent number: 11215913
    Abstract: A projector drive circuit includes a first voltage converter, a light source driver, a second voltage converter, and an isolation circuit. The first voltage converter converts a first voltage into a second voltage. The light source driver converts the second voltage into a third voltage. The second voltage converter converts the second voltage into a fourth voltage. The control circuit, coupled to the second voltage converter, receives the fourth voltage and outputs a first control signal. The isolation circuit, coupled to the control circuit and the light source driver, receives the first control signal and generates a second control signal to the light source driver, which controls the light source driver to generate the third voltage and provide the third voltage to a light source according to the second control signal. The isolation circuit electrically isolates the control circuit from the light source driver.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: January 4, 2022
    Assignee: Qisda Corporation
    Inventors: Chih-Hsiang Wu, Chi-Jen Chen
  • Patent number: 11206833
    Abstract: The present disclosure discloses a ceramic material having a positive slow release effect and a method for manufacturing the same. The ceramic material comprises a hierarchically meso-macroporous structure which composition at least includes silicon and oxygen, wherein the hierarchically meso-macroporous structure includes a plurality of macropores and a wall having a plurality of arranged mesopores, and the plurality of macropores are separated by the wall; and nano-scale metal particles confined in at least one of the plurality of arranged mesopores. The nano-scale metal particles have a positive slow release effect from the at least one of the plurality of arranged mesopores. The ceramic material has a property of inhibiting growth of microorganisms or killing the microorganisms in an environment or a system containing a hydrophilic medium.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 28, 2021
    Assignee: KAOHSIUNG MEDICAL UNIVERSITY
    Inventors: Chi-Jen Shih, Jung-Chang Kung, Pei-Shan Lu, Hao-Che Hsieh
  • Publication number: 20210391186
    Abstract: A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Liang-Guang Chen, Kei-Wei Chen, Hung Yen, Ting-Hsun Chang, Chi-Hsiang Shen, Li-Chieh Wu, Chi-Jen Liu
  • Publication number: 20210391208
    Abstract: A method for CMP includes following operations. A metal layer is received. A CMP slurry composition is provided in a CMP apparatus. The CMP slurry composition includes at least a first oxidizer and a second oxidizer different from each other. The first oxidizer is oxidized to form a peroxidant by the second oxidizer. A portion of the metal layer is oxidized to form a first metal oxide by the peroxidant. The first metal oxide is re-oxidized to form a second metal oxide by the second oxidizer.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Chi-Hsiang Shen, Ting-Hsun Chang, Li-Chieh Wu, Hung Yen, Chi-Jen Liu, Liang-Guang Chen, Kei-Wei Chen
  • Publication number: 20210371702
    Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.
    Type: Application
    Filed: January 5, 2021
    Publication date: December 2, 2021
    Inventors: JI CUI, CHI-JEN LIU, LIANG-GUANG CHEN, KEI-WEI CHEN, CHUN-WEI HSU, LI-CHIEH WU, PENG-CHUNG JANGJIAN, KAO-FENG LIAO, FU-MING HUANG, WEI-WEI LIANG, TANG-KUEI CHANG, HUI-CHI HUANG
  • Publication number: 20210330648
    Abstract: Disclosed is a pharmaceutical composition comprising: an active ingredient of the following formula (I) or a pharmaceutically acceptable salt or solvate thereof present in an amount of 8 wt % to 30 wt %: and two or more excipients at least including a dispersant and a solubilizer present in an amount of 70 wt % to 92 wt %. Also disclosed are methods for reducing the glycemic level and treating disorders associated with glucagon with the aforesaid pharmaceutical composition.
    Type: Application
    Filed: July 2, 2021
    Publication date: October 28, 2021
    Inventors: Chi-Jen HONG, Yen-Fu CHEN, Cheng-Ho CHUNG
  • Patent number: 11133247
    Abstract: A semiconductor device includes a first dielectric layer over a substrate, the first dielectric layer including a first dielectric material extending from a first side of the first dielectric layer distal from the substrate to a second side of the first dielectric layer opposing the first side; a second dielectric layer over the first dielectric layer; a conductive line in the first dielectric layer, the conductive line including a first conductive material, an upper surface of the conductive line being closer to the substrate than an upper surface of the first dielectric layer; a metal cap in the first dielectric layer, the metal cap being over and physically connected to the conductive line, the metal cap including a second conductive material different from the first conductive material; and a via in the second dielectric layer and physically connected to the metal cap, the via including the second conductive material.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Ho, Chun-Wei Hsu, Chi-Hsiang Shen, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, William Weilun Hong, Liang-Guang Chen, Kei-Wei Chen
  • Publication number: 20210289852
    Abstract: A face mask structure and a method of manufacturing the same are provided. The face mask structure includes a main structure layer and an elastic structure layer. The elastic structure layer is disposed on a surface layer of the main structure layer so as to fully cover the surface layer. The elastic structure layer includes an elastic ear strap layer partially separatably disposed on the surface layer of the main structure layer, the elastic ear strap layer includes two elastic ear strap portions separatably connected with each other through a tear-off line. Each of the two elastic ear strap portions has two opposite ends separated from each other. After the two elastic ear strap portions are separated from each other by ripping or tearing along the tear-off line, two ears of a user can respectively wear the two elastic ear strap portions when using the face mask structure.
    Type: Application
    Filed: May 7, 2020
    Publication date: September 23, 2021
    Inventors: CHIEN-SHOU LIAO, CHI-JEN LAN, KUO-PIN CHUAN, JUNG-CHIN SHEN, CHUN-YI WU
  • Patent number: 11121028
    Abstract: Semiconductor devices and methods of forming are provided. In some embodiments the semiconductor device includes a substrate, and a dielectric layer over the substrate. A first conductive feature is included in the dielectric layer, the first conductive feature comprising a first number of material layers. A second conductive feature is included in the dielectric layer, the second conductive feature comprising a second number of material layers, where the second number is higher than the first number. A first electrical connector is included overlying the first conductive feature.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wei Hsu, Ling-Fu Nieh, Pinlei Edmund Chu, Chi-Jen Liu, Yi-Sheng Lin, Ting-Hsun Chang, Chia-Wei Ho, Liang-Guang Chen
  • Publication number: 20210280530
    Abstract: Provided is an electronic package, including a multi-chip packaging body with a plurality of electronic elements and a stress buffer layer disposed on the multi-chip packaging body. The stress buffer layer is in contact with the plurality of electronic elements so as to cause stresses to be evenly distributed in the stress buffer layer instead of being concentrated in specific areas, thereby preventing structural stresses from being concentrated in corners of the electronic elements.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 9, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Jen Chen, Chih-Hsun Hsu, Chee-Key Chung, Jia-Wei Pan, Chang-Fu Lin
  • Publication number: 20210277558
    Abstract: A portable patchwork sewing tool kit includes: a base plate, the inner face thereof is provided with a first page and a second page which can be folded or unfolded optionally; a rotary cutting mat fixed to the first page, the rotary cutting mat comprises a bottom plate and a cutting plate pad screwed on the bottom plate through a pivot joint base to be rotated under stress; a detachable ironing mat fixed to the second page, including a core board, a cotton spreading layer covering the core board and a cotton fabric surface layer covering the cotton spreading layer, an ironing face formed outside the cotton fabric surface layer; and a plurality of pushing edges formed around the cutting plate pad and spaced apart.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 9, 2021
    Inventor: Chi-Jen CHEN
  • Patent number: 11114339
    Abstract: A method of manufacturing a device includes exposing at least one of a source/drain contact plug or a gate contact plug to a metal ion source solution during a manufacturing process, wherein a constituent metal of a metal ion in the metal ion source solution and the at least one source/drain contact plug or gate contact plug is the same. If the source/drain contact plug or the gate contact plug is formed of cobalt, the metal ion source solution includes a cobalt ion source solution. If the source/drain contact plug or the gate contact plug is formed of tungsten, the metal ion source solution includes a tungsten ion source solution.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ling-Fu Nieh, Chun-Wei Hsu, Pinlei Edmund Chu, Chi-Jen Liu, Liang-Guang Chen, Yi-Sheng Lin
  • Publication number: 20210272818
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Application
    Filed: May 18, 2021
    Publication date: September 2, 2021
    Inventors: Yi-Sheng LIN, Chi-Jen LIU, Chi-Hsiang SHEN, Te-Ming KUNG, Chun-Wei HSU, Chia-Wei HO, Yang-Chun CHENG, William Weilun HONG, Liang-Guang CHEN, Kei-Wei CHEN
  • Patent number: 11094555
    Abstract: The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wei Hsu, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Yang-Chun Cheng