Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.

Abstract: A water cooling head with sparse and dense fins, including a main body, a first fin set and a second fin set. Wherein a chamber is formed inside the main body, the main body has a first plate and a second plate, the main body forms an inlet channel and an outlet channel, so that the cooling water passes through the chamber. The first fin set and the second fin set are arranged in the chamber, and the first fin set and the second fin set are connected to the first plate respectively. The first fin set comprises several first fins spaced apart, the first fins divide the chamber to form several first channels. The second fin set comprises several second fins spaced apart, the second fins divide the chamber to form several second channels. The water cooling head can increase the overall heat sinking efficiency.

Abstract: A portable electronic device including a first body, a second body, a stand, and a hinge structure is provided. The stand has a first pivot part and a second pivot part opposite to the first pivot part, wherein the first pivot part is pivotally connected to the first body, and the second body is pivotally connected to the second pivot part. The hinge structure includes a first bracket secured to the second body, a second bracket secured to the second pivot part of the stand, a first movable base, a first shaft secured to the first bracket and pivoted to the first movable base, a second movable base, a second shaft secured to the first movable base and pivoted to the second movable base, and a sliding shaft fixed to the second movable base and slidably connected to the second bracket.

Abstract: The present disclosure provides a time delay integration (TDI) sensor using a rolling shutter. The TDI sensor includes multiple pixel columns. Each pixel column includes multiple pixels arranged in an along-track direction, wherein two adjacent pixels or two adjacent pixel groups in every pixel column have a separation space therebetween. The separation space is equal to a pixel height multiplied by a time ratio of a line time difference of the rolling shutter and a frame period, or equal to a summation of at least one pixel height and a multiplication of the pixel height by the time ratio of the line time difference and the frame period. The TDI sensor further records defect pixels of a pixel array such that in integrating pixel data to integrators, the pixel data associated with the defect pixels is not integrated into corresponding integrators.

Abstract: The present invention provides a resonant switched capacitor voltage converter (RSCC), which is coupled to and operates synchronously with another RSCC. The RSCC includes: plural switches, a resonant inductor, a resonant capacitor, and a control circuit. The control circuit controls the switches, so that the resonant capacitor and the resonant inductor are connected in series to each other, to perform resonant operation in a switching period, thus converting an input voltage to an output voltage. The control circuit generates a zero current signal and a first synchronization signal when a resonant inductor current flowing through the resonant inductor is zero. The control circuit turns off at least one corresponding switch according to the zero current signal. The control circuit turns on at least one corresponding switch according to the zero-current signal and a second synchronization signal, so that the RSCC operates in synchronization with at least another RSCC.

Abstract: An immersion cooling system includes a pressure seal tank, an electronic apparatus, a pressure balance pipe and a relief valve. The pressure seal tank is configured to store coolant. A vapor space is formed in the pressure seal tank above the liquid level of the coolant. The electronic apparatus is completely immersed in the coolant. The pressure balance pipe has a gas collection length. The first port of the pressure balance pipe is disposed on the top surface of the pressure seal tank. The relief valve is disposed on the second port of the pressure balance pipe. The second port is farther away from the top surface of the pressure seal tank than the first port. The gas collection length of the pressure equalization tube allows the concentration of vaporized coolant at the first port to be greater than the concentration of vaporized coolant at the second port.

Abstract: An electronic device including a substrate, a gate line, a switch element, and a photodetector is provided. The gate line is disposed on the substrate. The switch element is disposed on the substrate and is electrically connected to the gate line. The photodetector is disposed on the substrate and electrically connected to the switch element. The photodetector includes a first semiconductor. In a cross-sectional view of the electronic device, a sidewall of the first semiconductor and the gate line are spaced from each other by a first distance. The first distance is greater than or equal to 2 micrometers and less than or equal to 6 micrometers.

Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.

Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random access memory (FeRAM) device is over the substrate between the select gate and the first source/drain region. A transistor device is disposed on an upper surface of the substrate. The substrate has a recessed surface that is below the upper surface of the substrate and that is laterally separated from the upper surface of the substrate by a boundary isolation structure extending into a trench within the upper surface of the substrate. The FeRAM device is arranged over the recessed surface.

Abstract: A method of manufacturing an electronic device, including the following steps, is provided. A first dielectric layer and a second dielectric layer are provided. The first dielectric layer has a first surface and a second surface opposite to each other, and the second dielectric layer has a third surface and a fourth surface opposite to each other. A first unit is formed on the first surface or the second surface of the first dielectric layer. The first dielectric layer and the second dielectric layer are combined to form a substrate structure. The second surface of the first dielectric layer faces the third surface of the second dielectric layer. A dielectric loss of the first unit is less than a dielectric loss of the first dielectric layer. The method of manufacturing the electronic device of the embodiment of the disclosure can reduce the dielectric loss by using the unit.

Abstract: A vehicle device setting method including: capturing, by an image sensing unit, a first image frame; recognizing a user ID according to the first image frame; showing ID information of the recognized user ID on a screen or by a speaker; capturing a second image frame; generating a confirm signal when a first user expression is recognized by calculating an expression feature in the second image frame and comparing the recognized expression feature with stored expression data associated with a predetermined user expression to confirm whether the recognized user ID is correct or not according to the second image frame captured after the ID information is shown; controlling an electronic device according to the confirm signal; and entering a data update mode instructed by the user and updating setting information of the electronic device by current electronic device setting according to a saving signal generated by confirming a second user expression in a third image frame captured after the user ID is confirmed

Abstract: A laser machining device includes a pulsed laser generator, an accommodation chamber, a bandwidth broadening unit and a pulse compression unit. The pulsed laser generator is configured to emit a pulsed laser. The accommodation chamber has a gas inlet. The bandwidth broadening unit is disposed in the accommodation chamber, and is configured to broaden a frequency bandwidth of the pulsed laser to obtain a broad bandwidth pulsed laser. The pulse compression unit is disposed in the accommodation chamber. The bandwidth broadening unit and the pulse compression unit are arranged in order along a laser propagation path, and the pulse compression unit is configured to compress a pulse duration of the broad bandwidth pulsed laser.

Abstract: An electronic device including a substrate, a first electrode layer, a photodiode, an insulating layer, a second electrode layer, and a first transparent conductive layer is provided. The first electrode layer is disposed on the substrate. The photodiode is disposed on the first electrode layer and is electrically connected to the first electrode layer. The insulating layer is disposed on the photodiode. The second electrode layer is disposed on the insulating layer and is electrically connected to the photodiode. The first transparent conductive layer is disposed on the insulating layer and contacts the second electrode layer. A manufacturing method of an electronic device is also provided.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.

Abstract: A quick connect structure having a fitting connector, a connector, and U-shaped positioning snap pin. The fitting connector has a connector part, a fitting connector body part coupled to the connector part, and a fitting part coupled to the fitting connector. The connector part, the fitting connector body part, and the fitting part define a fitting hole extending therethrough, and the fitting part defines positioning groove, a longitudinal snap hole, and a side snap opening in communication with the longitudinal snap hole. The connector has a connection end, a connector body part coupled to the connection end, and a positioning bump. The connection end and the connector body part define a duct hole extending therethrough, the connection end defines a positioning snap groove, and the fitting connector is configured to accept the connection end in the fitting hole.

Abstract: A real time Taq-Man PCR assay for detecting multiple serotypes of human papillomavirus (HPV) wherein the number of serotypes detected exceeds the number of colorimetric channels for detection. A biological sample is combined with three oligonucleotide primer/probe sets such that the probes and primers anneal to a target sequence. Each primer/probe set is at least preferential for a specific serotype of an organism. The first and second primer/probe sets are degenerate with respect to each other. The third primer/probe set is not degenerate with respect to the first and second primer/probe sets and discriminates for a third serotype. The third primer/probe set has a signal moiety that emits signal at a wavelength that is the same or different from the wavelength emitted by the signal moiety of the degenerate primer/probe set probes. The target sequences, if present, are amplified and detected.

Abstract: An apparatus comprises a processing device configured to identify storage workloads to be run on a storage system, and to determine a mix of input/output (TO) patterns associated with the identified storage workloads, the mix of IO patterns comprising a first set of IO patterns characterizing types of IO operations performed by a first storage workload and at least a second set of IO patterns characterizing types of IO operations performed by a second storage workload. The processing device is also configured to calculate an affinity metric for the mix of IO patterns, the calculated affinity metric characterizing a difference between (i) performance metrics for the mix of IO patterns running concurrently and (ii) the first and second sets of IO patterns running individually. The processing device is further configured to allocate the identified storage workloads to storage devices of the storage system based on the calculated affinity metric.

Abstract: An asymmetric half-bridge converter is provided. The asymmetric half-bridge converter includes a switch circuit, a resonance tank, a current sensor, and a controller. The current sensor senses a waveform of a resonance current flowing through the resonance tank to generate a sensing result. The controller determines the sensing result. When the sensing result indicates that an ending current value of a primary resonance waveform of the resonance current is greater than a predetermined value, the controller performs a first switching operation on the switch circuit. When the sensing result indicates that the ending current value of the primary resonance waveform is less than or equal to the predetermined value, the controller performs a second switching operation on the switch circuit.

Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.