Abstract: A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT <10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT <1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.

Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

Abstract: CVD dielectric materials are generally preferred for anti-reflection coatings because their optical properties can be varied both by controlling composition and by suitable surface treatment. In prior art films of this type it can be difficult to control both the refractive index and the extinction coefficient simultaneously. The present invention shows how optical properties can be tailored to meet a range of predetermined values by depositing each dielectric anti-reflection coating as a series of sub-coatings. After each sub-coating has been deposited it is subjected to surface treatment through exposure to a gaseous plasma, thereby forming an interface layer which provides a wider window for fine tuning RI and K values. Generally the finished film will comprise 3-5 of these sub-coatings. Software simulation is used to determine the precise composition for each sub-layer as well as the optical properties of the DARC film.

Abstract: A method for forming a dielectric layer provides that a oxidizable substrate has formed thereupon a thermal oxide layer in turn having formed thereupon a deposited nitride layer. The deposited nitride/thermal oxide stack layer is then sequentially: (1) annealed within a nitriding atmosphere; (2) annealed within an oxidizing atmosphere; and (3) treated with a vaporous hydrofluoric acid atmosphere. The annealed and treated stack layer provides, for example, a gate dielectric layer with diminished thickness and enhanced performance.

Abstract: A method of forming a highly uniform ultra-thin insulating gate oxide layer on a silicon wafer is presented where an oxide layer non-uniformity introduced at a processing temperature is compensated during a cooling step during which oxygen is added to give additional oxide layer growth thereby producing a substantially uniform oxide layer.

Abstract: A method of forming a highly uniform ultra-thin insulating gate oxide layer on a silicon wafer is presented where an oxide layer non-uniformity introduced at a processing temperature is compensated during a cooling step during which oxygen is added to give additional oxide layer growth thereby producing a substantially uniform oxide layer.

Abstract: A method of reducing the boron-penetrating of effect in a CMOS transistor provides a silicon substrate, which comprises an isolating area, an active area and a gate oxide layer formed on the silicon substrate in the active layer. A polysilicon layer is then deposited on the silicon substrate. Next, boron ions (B+) are doped into the polysilicon layer. Next, a gate photoresist with a predetermined gate pattern is formed on the polysilicon layer. The polysilicon not covered by the gate photoresist is then etched to form a polysilicon gate. The gate photoresist is used as a mask to dope boron difluoride ions (BF2+) into the silicon substrate. Finally, after removing the gate photoresist, a tempering procedure is performed to form a shallow junction area of a source/drain region on the silicon substrate.

Abstract: A method of forming a gate oxide layer with improved ability to resist process damage increases the reliability and yield of a transistor device. First, a nitrogen-containing gate oxide layer is formed on an element area of a silicon substrate. Then, a polysilicon layer is deposited on the gate oxide layer. Next, a gate doping process and a fluorine ion implantation are performed on the polysilicon layer. Then, a high-temperature tempering procedure is performed to make the fluorine enter the gate oxide layer.

Abstract: A method of reducing the boron-penetrating effect in a CMOS transistor provides a silicon substrate, which comprises an isolating area, an active area and a gate oxide layer formed on the active layer. A polysilicon layer is then deposited on the silicon substrate. Next, the boron ion (B+) is doped into the polysilicon layer. Next, a gate photoresist with a predetermined gate pattern is formed on the polysilicon layer. The polysilicon not covered by the gate photoresist is then etched to from a polysilicon gate. The gate photoresist is used as a mask to dope the boron-fluorine ion (BF2+) into the silicon substrate. Finally, after removing the gate photoresist, a tempering procedure is performed to form a shallow junction area of a source/drain on the silicon substrate.

Abstract: A method of forming a gate oxide layer with improved ability to resist process damage increases the reliability and yield of a transistor device. First, a nitrogen-containing gate oxide layer is formed on an element area of a silicon substrate. Then, a polysilicon layer is deposited on the gate oxide layer. Next, a gate doping process and a fluorine ion implantation are performed on the polysilicon layer. Then, a high-temperature tempering procedure is performed to make the fluorine enter the gate oxide layer.