Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

Abstract: A method of forming dual gate insulator layers, each with a specific insulator thickness, featuring a HF type pre-clean procedure performed prior to formation of each of the gate insulator layers, has been developed. After a first HF type pre-clean procedure a silicon nitride layer is deposited on the native oxide free, semiconductor substrate followed by selective removal of silicon nitride layer from a second portion of the semiconductor substrate. After a second HF type pre-clean procedure a silicon dioxide gate insulator layer is formed on the second portion of the native oxide free, semiconductor substrate, with the silicon dioxide gate insulator layer comprised with a different thickness than the silicon nitride gate insulator layer, located on a first portion of the semiconductor substrate. The procedure used to form the silicon dioxide gate insulator layer also removes bulk traps in the silicon nitride gate insulator layer.

Abstract: A method of defining a conductive gate structure for a MOSFET device wherein the etch rate selectivity of the conductive gate material to an underlying insulator layer is optimized, has been developed. After formation of a nitrided silicon dioxide layer, to be used as for the MOSFET gate insulator layer, a high temperature hydrogen anneal procedure is performed. The high temperature anneal procedure replaces nitrogen components in a top portion of the nitrided silicon dioxide gate insulator layer with hydrogen components. The etch rate of the hydrogen annealed layer in specific dry etch ambients is now decreased when compared to the non-hydrogen annealed nitrided silicon dioxide counterpart. Thus the etch rate selectivity of conductive gate material to underlying gate insulator material is increased when employing the slower etching hydrogen annealed nitrided silicon dioxide layer.

Abstract: A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT<10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT<1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.

Abstract: A method of forming a final stacked gate dielectric comprising the following steps. A substrate is provided and an oxide layer is formed upon the substrate. A nitride layer is formed upon the oxide layer. The oxide layer and the nitride layer comprising an initial stacked gate dielectric. The initial stacked gate dielectric is subjected to a plasma nitridation process under an N-containing ambient to form an intermediate stacked gate dielectric. The intermediate stacked gate dielectric is subjected to a plasma reoxidation process to form the final stacked gate dielectric.

Abstract: A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.

Abstract: A method of determining a composition of an integrated circuit feature, including collecting intensity data representative of spectral wavelengths of radiant energy generated by a plasma during plasma nitridation of an integrated circuit feature disposed on a substrate, analysing the in intensity data to determine a peak intensity at one of the wavelengths, and determining a component concentration of the feature based on the peak intensity.

Abstract: A method of determining a composition of an integrated circuit feature, including collecting intensity data representative of spectral wavelengths of radiant energy generated by a plasma during plasma nitridation of an integrated circuit feature disposed on a substrate, analyzing the intensity data to determine a peak intensity at one of the wavelengths, and determining a component concentration of the feature based on the peak intensity.

Abstract: A method of forming dual gate insulator layers, each with a specific insulator thickness, featuring a HF type pre-clean procedure performed prior to formation of each of the gate insulator layers, has been developed. After a first HF type pre-clean procedure a silicon nitride layer is deposited on the native oxide free, semiconductor substrate followed by selective removal of silicon nitride layer from a second portion of the semiconductor substrate. After a second HF type pre-clean procedure a silicon dioxide gate insulator layer is formed on the second portion of the native oxide free, semiconductor substrate, with the silicon dioxide gate insulator layer comprised with a different thickness than the silicon nitride gate insulator layer, located on a first portion of the semiconductor substrate. The procedure used to form the silicon dioxide gate insulator layer also removes bulk traps in the silicon nitride gate insulator layer.

Abstract: CVD dielectric materials are generally preferred for anti-reflection coatings because their optical properties can be varied both by controlling composition and by suitable surface treatment. In prior art films of this type it can be difficult to control both the refractive index and the extinction coefficient simultaneously. The present invention shows how optical properties can be tailored to meet a range of predetermined values by depositing each dielectric anti-reflection coating as a series of sub-coatings. After each sub-coating has been deposited it is subjected to surface treatment through exposure to a gaseous plasma, thereby forming an interface layer which provides a wider window for fine tuning RI and K values. Generally the finished film will comprise 3-of these sub-coatings. Software simulation is used to determine the precise composition for each sub-layer as well as the optical properties of the DARC film.

Abstract: Novel methods for improving the within-wafer uniformity of a gate oxide layer on a semiconductor wafer substrate. According to a first embodiment, a gate oxide layer is formed on a wafer using conventional oxidation parameters and equipment. Next, the edge-thick gate oxide layer is nitridated using a center-thick plasma nitridation profile to enhance uniformity in thickness of the gate oxide layer between the center region and the edge or peripheral regions of the wafer. According to a second embodiment, the wafer substrate is first nitridated and then oxidized to form the gate oxide layer. The nitrogen incorporated into the wafer surface during the nitridation step retards oxidation of the wafer at the wafer edge to enhance uniformity in thickness of the gate oxide layer between the center region and the edge or peripheral regions of the wafer.

Abstract: A new method and sequence is provided for the polishing of the surface of a layer of metal containing copper. The invention provides for an improved method of residue removal. The invention improves the removal of slurry as part of the step of applying DIW by, during the step of applying DIW, raising the wafer carrier, thus allowing uninhibited removal of the slurry from the surface that is being polished.

Abstract: The present disclosure provides a method for forming and manufacturing a silicon germanium (SiGe) based device. After forming a substrate of the device and forming one or more layers of semiconductor processing materials in one or more predetermined locations to establish an opening for depositing one or more SiGe material layers, a pre-baking process is applied to the device under a low pressure not to exceed 79 torr and 900° C. Once completed, the one or more SiGe material layers are deposited and other conventional steps are taken to complete the manufacturing of the device.

Abstract: The present disclosure provides a method for forming a gate stack structure for semiconductor devices. The disclosed method comprises steps such as forming a dielectric layer on a substrate; applying a plasma nitridation process on the formed dielectric layer; applying a first anneal process on the deposited dielectric layer; etching the dielectric layer to a predetermined thickness using a diluted etchant; applying a second anneal process using an oxygen environment on the etched dielectric layer after the etching; and forming a gate electrode layer on top of the dielectric layer. The etching makes the top portion of the etched dielectric layer have a significantly higher concentration of nitrogen than the lower portion of the etched dielectric layer so as the leakage current is significantly reduced.

Abstract: A new method and sequence is provided for the polishing of the surface of a layer of metal containing copper. One of the main problems that is conventionally encountered during the polishing of a copper surface is insufficient removal of the slurry and the therein contained residue of semiconductor materials. The invention therefore provides for an improved method of residue removal. Using the conventional step of applying DIW, the contact between the polishing pad and the surface that is being polished is constant and uninterrupted during the step of applying DIW. The invention improves the removal of slurry as part of the step of applying DIW by, during the step of applying DIW, raising the wafer carrier, thus allowing uninhibited removal of the slurry from the surface that is being polished.

Abstract: A process for forming a dielectric stack for use as a gate dielectric layer for sub −0.1 um MOSFET devices has been developed. The process features growth of a thin silicon nitride layer on the surface of a semiconductor substrate via a low temperature plasma nitridization procedure. The conditions used allow a self-limiting silicon nitride layer, in regards to thickness, to be realized. A plasma oxidation procedure is next used to remove bulk traps in the silicon nitride layer in addition to forming a thin silicon oxide layer on the semiconductor surface, underlying the thin silicon nitride layer. The plasma oxidation procedure also results in conversion of a top portion of the silicon layer to silicon oxynitride, thus resulting in a dielectric gate stack comprised of silicon oxynitride-silicon oxide-silicon nitride.

Abstract: A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT<10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT<1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.

Abstract: A process for forming a dielectric stack for use as a gate dielectric layer for sub-0.1 um MOSFET devices has been developed. The process features growth of a thin silicon nitride layer on the surface of a semiconductor substrate via a low temperature plasma nitridization procedure. The conditions used allow a self-limiting silicon nitride layer, in regards to thickness, to be realized. A plasma oxidation procedure is next used to remove bulk traps in the silicon nitride layer in addition to forming a thin silicon oxide layer on the semiconductor surface, underlying the thin silicon nitride layer. The plasma oxidation procedure also results in conversion of a top portion of the silicon layer to silicon oxynitride, thus resulting in a dielectric gate stack comprised of silicon oxynitride-silicon oxide-silicon nitride.

Abstract: Novel methods for improving the within-wafer uniformity of a gate oxide layer on a semiconductor wafer substrate. According to a first embodiment, a gate oxide layer is formed on a wafer using conventional oxidation parameters and equipment. Next, the edge-thick gate oxide layer is nitridated using a center-thick plasma nitridation profile to enhance uniformity in thickness of the gate oxide layer between the center region and the edge or peripheral regions of the wafer. According to a second embodiment, the wafer substrate is first nitridated and then oxidized to form the gate oxide layer. The nitrogen incorporated into the wafer surface during the nitridation step retards oxidation of the wafer at the wafer edge to enhance uniformity in thickness of the gate oxide layer between the center region and the edge or peripheral regions of the wafer.

Abstract: A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT <10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT <1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.