Abstract: A method for fabricating a semiconductor device comprises providing a silicon-containing substrate with first, second, and third regions. First, second, and third gate stacks respectively overlie a portion of the silicon-containing substrate in the first, second, and third regions. A spacer is formed on opposing sidewalls of each of the first, second, and third gate stacks, the spacer overlying a portion of the silicon-containing substrate in the first, second, and third regions, respectively. A source/drain region is formed in a portion of the silicon-containing substrate in the first, second, and third regions, with the source/drain region adjacent to the first, second, and third gate stacks, respectively. The first, second, and third gate stacks have first, second, and third gate dielectric layers of various thicknesses and at least one thereof with a relatively thin thickness is treated by NH3-plasma, having a nitrogen-concentration of about 1013˜1021 atoms/cm2 therein.

Abstract: A method of forming an integrated circuit is provided. The method includes performing a multiple-time flash anneal process to a wafer, wherein the multiple-time flash anneal process comprises preheating the wafer to a first preheat temperature; performing a first flash on the wafer with a first flash energy; preheating the wafer to a second preheat temperature; and performing a second flash on the wafer with a second flash energy.

Abstract: A semiconductor structure includes a PMOS device and an NMOS device. The PMOS device includes a first gate dielectric on a semiconductor substrate, a first gate electrode on the first gate dielectric, and a first gate spacer along sidewalls of the first gate electrode and the first gate dielectric. The NMOS device includes a second gate dielectric on the semiconductor substrate, a second gate electrode on the second gate dielectric, a nitrided polysilicon re-oxidation layer having a vertical portion and a horizontal portion wherein the vertical portion is on sidewalls of the second gate electrode and the second gate dielectric and wherein the horizontal portion is on the semiconductor substrate, and a second gate spacer on sidewalls of the second gate electrode and the second gate dielectric, wherein the second gate spacer is on the horizontal portion of the nitrided polysilicon re-oxidation layer.

Abstract: A method of forming a gate dielectric layer includes forming a gate dielectric layer over a substrate. The gate dielectric layer is processed with carbon-containing ions. The gate dielectric layer is thermally processed, thereby providing the gate dielectric layer with a level of carbon between about 1 atomic % and about 20 atomic %.

Abstract: A method for stripping photoresist and cleaning a semiconductor substrate include a high temperature stripping process in a freshly mixed SPM solution followed by cleaning in a water soluble organic co-solvent such as acetone, IPA, methanol, ethanol, butanol, or DMSO. The substrate may undergo back side heating during the SPM solution stripping process and may optionally use nanospraying techniques to direct the water soluble organic co-solvent to the substrate. The method completely strips plasma hardened photoresist using only wet chemical operations.

Abstract: A fan control system includes a power source, a switch control circuit, a switch control signal delivering unit and a fan circuit module. The power source outputs a nominal power, the switch control circuit electrically connects to the power source, the switch control signal delivering unit electrically connects to the switch control circuit and can send a power control signal to the switch control circuit, and the fan circuit module electrically connects to the switch control circuits. In an initial operation state, the nominal power output from the power source can be reduced to a control power sending to the fan circuit module via the switch control circuit to drive at least one fan within the fan circuit module, and then the power control signal controls the control power after the switch control signal delivering unit sends the power control signal to the switch control circuit.

Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

Abstract: A cleaning sequence usable in semiconductor manufacturing efficiently cleans semiconductor substrates while preventing chemical oxide formation thereon. The sequence includes the sequence of: 1) treating with an HF solution; 2) treating with pure H2SO4; 3) treating with an H2O2 solution; 4) a DI water rinse; and 5) treatment with an HCl solution. The pure H2SO4 solution may include an H2SO4 concentration of about ninety-eight percent (98%) or greater. After the HCl solution treatment, the cleaned surface may be a silicon surface that is free of a chemical oxide having a thickness of 5 angstroms or greater. The invention finds particular advantage in semiconductor devices that utilize multiple gate oxide thicknesses.

Abstract: The preferred embodiment of the present invention provides a novel method of forming MOS devices using hydrogen annealing. The method includes providing a semiconductor substrate including a first region and a second region, forming at least a portion of a first MOS device covering at least a portion of the first active region, performing a hydrogen annealing in an ambient containing substantially pure hydrogen on the semiconductor substrate. The hydrogen annealing is performed after the step of the at least a portion of the first MOS device is formed, and preferably after a pre-oxidation cleaning. The method further includes forming a second MOS device in the second active region after hydrogen annealing. The hydrogen annealing causes the surface of the second active region to be substantially rounded, while the surface of the first active region is substantially flat.

Abstract: A method of defining a conductive gate structure for a MOSFET device wherein the etch rate selectivity of the conductive gate material to an underlying insulator layer is optimized, has been developed. After formation of a nitrided silicon dioxide layer, to be used as for the MOSFET gate insulator layer, a high temperature hydrogen anneal procedure is performed. The high temperature anneal procedure replaces nitrogen components in a top portion of the nitrided silicon dioxide gate insulator layer with hydrogen components. The etch rate of the hydrogen annealed layer in specific dry etch ambients is now decreased when compared to the non-hydrogen annealed nitrided silicon dioxide counterpart. Thus the etch rate selectivity of conductive gate material to underlying gate insulator material is increased when employing the slower etching hydrogen annealed nitrided silicon dioxide layer.

Abstract: A metal-oxide-semiconductor field-effect transistors (MOSFET) with a gate structure having a deuterated layer is provided. In accordance with embodiments of the present invention, a transistor comprises the deuterated layer formed over a gate dielectric layer. A gate electrode is formed over the deuterated layer. The deuterated layer prevents or reduces dopant penetration into a substrate from the gate electrode. The deuterated layer may be, for example, formed by a thermal process in an ambient of a deuterated gas, such as deuterated ammonia. The deuterated layer may also be formed by a nitridation process using deuterated ammonia.

Abstract: A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.

Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

Abstract: A method of forming dual gate insulator layers, each with a specific insulator thickness, featuring a HF type pre-clean procedure performed prior to formation of each of the gate insulator layers, has been developed. After a first HF type pre-clean procedure a silicon nitride layer is deposited on the native oxide free, semiconductor substrate followed by selective removal of silicon nitride layer from a second portion of the semiconductor substrate. After a second HF type pre-clean procedure a silicon dioxide gate insulator layer is formed on the second portion of the native oxide free, semiconductor substrate, with the silicon dioxide gate insulator layer comprised with a different thickness than the silicon nitride gate insulator layer, located on a first portion of the semiconductor substrate. The procedure used to form the silicon dioxide gate insulator layer also removes bulk traps in the silicon nitride gate insulator layer.

Abstract: A method of defining a conductive gate structure for a MOSFET device wherein the etch rate selectivity of the conductive gate material to an underlying insulator layer is optimized, has been developed. After formation of a nitrided silicon dioxide layer, to be used as for the MOSFET gate insulator layer, a high temperature hydrogen anneal procedure is performed. The high temperature anneal procedure replaces nitrogen components in a top portion of the nitrided silicon dioxide gate insulator layer with hydrogen components. The etch rate of the hydrogen annealed layer in specific dry etch ambients is now decreased when compared to the non-hydrogen annealed nitrided silicon dioxide counterpart. Thus the etch rate selectivity of conductive gate material to underlying gate insulator material is increased when employing the slower etching hydrogen annealed nitrided silicon dioxide layer.

Abstract: A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT<10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT<1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.

Abstract: A method of forming a final stacked gate dielectric comprising the following steps. A substrate is provided and an oxide layer is formed upon the substrate. A nitride layer is formed upon the oxide layer. The oxide layer and the nitride layer comprising an initial stacked gate dielectric. The initial stacked gate dielectric is subjected to a plasma nitridation process under an N-containing ambient to form an intermediate stacked gate dielectric. The intermediate stacked gate dielectric is subjected to a plasma reoxidation process to form the final stacked gate dielectric.

Abstract: A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.

Abstract: A method of determining a composition of an integrated circuit feature, including collecting intensity data representative of spectral wavelengths of radiant energy generated by a plasma during plasma nitridation of an integrated circuit feature disposed on a substrate, analysing the in intensity data to determine a peak intensity at one of the wavelengths, and determining a component concentration of the feature based on the peak intensity.