Abstract: A distributed audio visual (AV) system including a plurality of media servers, a media renderer, and a control point which are connected to each other via a peer-to-peer network is provided. Each of the media servers includes a content directory management unit (CDMU) and a query content information (QCI) module, wherein the CDMU includes a synchronizer module and a content information maintainer (CIM) module. The synchronizer module synchronizes content information of AV contents stored in all the media servers. The CIM module records the content information and establishes an integrated content directory list according to the content information. The QCI module queries the content information. The control point obtains the integrated content directory list from one of the media servers and queries the content information related to all the AV contents, so as to control the media renderer to play the AV contents.

Abstract: In one embodiment, a method of growing a heteroepitaxial layer comprises providing a patterned substrate containing patterned features having sidewalls. The method also includes directing ions toward the sidewalls in an exposure, wherein altered sidewall regions are formed, and depositing the heteroepitaxial layer under a set of deposition conditions effective to preferentially promote epitaxial growth on the sidewalls in comparison to other surfaces of the patterned features.

Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

Abstract: A workpiece is implanted to a first depth to form a first amorphized region. This amorphized region is then etched to the first depth. After etching, the workpiece is implanted to a second depth to form a second amorphized region below a location of the first amorphized region. The second amorphized region is then etched to the second depth. The implant and etch steps may be repeated until structure is formed to the desired depth. The workpiece may be, for example, a compound semiconductor, such as GaN, a magnetic material, silicon, or other materials.

Abstract: An improved method of creating LEDs is disclosed. Rather than using a dielectric coating to separate the bond pads from the top surface of the LED, this region of the LED is implanted with ions to increase its resistivity to minimize current flow therethrough. In another embodiment, a plurality of LEDs are produced on a single substrate by implanting ions in the regions between the LEDs and then etching a trench, where the trench is narrower than the implanted regions and positioned within these regions. This results in a trench where both sides have current confinement capabilities to reduce leakage.

Abstract: The present disclosure provides a method that includes forming first and second gate structures over first and second regions, respectively, removing a first dummy gate and first dummy dielectric from the first gate structure thereby forming a first trench and removing a second dummy gate and second dummy dielectric from the second gate structure thereby forming a second trench, forming a gate layer to partially fill the first and second trenches, forming a material layer to fill the remainder of the first and second trenches, removing a portion of the material layer such that a remaining portion of the material layer protects a first portion of the gate layer located at a bottom portion of the first and second trenches, removing a second portion of the gate layer, removing the remaining portion of the material layer from the first and second trenches.

Abstract: A bandwidth arranging method includes the following steps of: registering isochronous packets of N isochronous streams, N is a natural number greater than 1; segmenting an isochronous transmission period into M sub-periods, M is a natural number greater than 1; arranging operation of transmitting each of the N isochronous streams in one of the M sub-periods and allocating corresponding bandwidth according to bandwidth requirement information corresponding to each of the N isochronous streams; arranging the isochronous packets into M output queues corresponding to the respective M sub-periods; outputting isochronous packets stored in the M output queues in the respective M sub-periods.

Abstract: A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.

Abstract: Ion implantation is used to form a current confinement structure, such as that in a light emitting diode. This current confinement structure defines multiple cells in one embodiment, each of which may surround an undoped region. The ion implantation may be performed between formation of the various layers. In one embodiment, the formation of one layer is interrupted and then resumed after ion implantation is performed.

Abstract: A method of manufacturing a semiconductor device comprising forming a gate oxide layer over a substrate subjecting the gate oxide layer to a first nitridation process, subjecting the gate oxide layer to a first anneal process after the first nitridation process, subjecting the gate oxide layer to a second nitridation process after the first anneal process, subjecting the gate oxide layer to a second anneal process after the second nitridation process, and forming a gate electrode over the gate oxide.

Abstract: A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.

Abstract: An improved method of creating LED arrays is disclosed. A p-type layer, multi-quantum well and n-type layer are disposed on a substrate. The device is then etched to expose portions of the n-type layer. To create the necessary electrical isolation between adjacent LEDs, an ion implantation is performed to create a non-conductive implanted region. In some embodiments, an implanted region extends through the p-type layer, MQW and n-type layer. In another embodiment, a first implanted region is created in the n-type layer. In addition, a second implanted region is created in the p-type layer and multi-quantum well immediately adjacent to etched n-type layer. In some embodiments, the ion implantation is done perpendicular to the substrate. In other embodiments, the implant is performed at an angle.

Abstract: An improved method of creating LEDs is disclosed. Rather than using a dielectric coating to separate the bond pads from the top surface of the LED, this region of the LED is implanted with ions to increase its resistivity to minimize current flow therethrough. In another embodiment, a plurality of LEDs are produced on a single substrate by implanting ions in the regions between the LEDs and then etching a trench, where the trench is narrower than the implanted regions and positioned within these regions. This results in a trench where both sides have current confinement capabilities to reduce leakage.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than one phosphorous atom. The n-type impurity may include phosphorous dimer or phosphorous tetramer.

Abstract: An improved method of fabricating a vertical semiconductor LED is disclosed. Ions are implanted into the LED to create non-conductive regions, which facilitates current spreading in the device. In some embodiments, the non-conductive regions are located in the p-type layer. In other embodiments, the non-conductive layer may be in the multi-quantum well or n-type layer.

Abstract: A lateral light emitting diode comprises a layer stack disposed on one side of a substrate, the layer stack including a p-type layer, n-type layer, and a p/n junction formed therebetween. The LED may further include a p-electrode disposed on a first side of the substrate and being in contact with the p-type layer on an exposed surface and an n-electrode disposed on the first side of the substrate and being in contact with an exposed surface of an n+ sub-layer of the n-type layer.

Abstract: A system and a method for transmitting network packets are provided. The system includes an information module, a scheduling module, and a forwarding module. The information module receives and records media information of a plurality of multimedia streams. The scheduling module calculates a guaranteed bit rate of each multimedia stream according to the media information provided by the information module, and rearranges isochronous packets of the multimedia streams in the first time slots of a plurality of clock cycles according to the guaranteed bit rates so that the transmission of the isochronous packets satisfies the guaranteed bit rates. The length of each clock cycle is a predetermined length. The length of the first time slot and the predetermined length are in a predetermined ratio. The forwarding module transmits all the packets of a clock cycle to a network at every a time interval of the predetermined length.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer.

Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each gate structure having a dummy gate, removing the dummy gate from the first, second, third, and fourth gate structures, thereby forming first, second, third, and fourth trenches, respectively, forming a metal layer to partially fill in the first, second, third, and fourth trenches, forming a first photoresist layer over the first, second, and third trenches, etching a portion of the metal layer in the fourth trench, removing the first photoresist layer, forming a second photoresist layer over the second and third trenches, etching the metal layer in the first trench and the remaining portion of the metal layer in the fourth trench, and removing the second photoresist layer.

Abstract: A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT<10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT<1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.