Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: The present invention relates to a foamable composition used to prepare foamed thermoplastic polyurethane and a microwave molded body thereof. The foamable composition includes unfoamed thermoplastic polyurethane particles, a thickener or a bridging agent, and a foaming agent, wherein the unfoamed thermoplastic polyurethane particles have a viscosity of 1,000 poise to 9,000 poise measured at 170° C. according to JISK 7311 test method.

Abstract: An electronic device is provided. The electronic device includes a substrate structure, a control unit, a first circuit structure, and an electronic unit. The substrate structure has a conductive via pattern and a dummy via pattern. The control unit is electrically connected to the conductive via pattern. The first circuit structure is electrically connected to the conductive via pattern. The electronic unit is electrically connected to the control unit through the first circuit structure. The dummy via pattern is electrically insulated from the first circuit structure.

Abstract: A semiconductor package device is provided. The semiconductor package device includes a chip and a redistribution layer disposed on the chip and electrically connected to the chip. The redistribution layer includes a plurality of first metal lines and a plurality of second metal lines, wherein at least one of the second metal lines is disposed between two adjacent first metal lines. The included angle between the at least one of the second metal lines and the two adjacent first metal lines is greater than or equal to 0 degrees and less than or equal to 10 degrees. The first width of one of the two adjacent first metal lines is greater than the second width of the at least one of the second metal lines.

Abstract: A three-dimensional data encoding method includes generating a bitstream by encoding subspaces included in a current space including three-dimensional points. In the generating of the bitstream: first information is stored in a first header which is common to the subspaces and included in the bitstream, the first information indicating first coordinates which are coordinates of the current space; and second information is stored in a second header which is provided on a subspace basis and included in the bitstream, the second information indicating a difference between second coordinates which are coordinates of a corresponding subspace among the subspaces and the first coordinates.

Abstract: An electronic device including a circuit structure, a bonding element and an electronic unit is disclosed. The circuit structure includes a conductive pad, and the conductive pad has an accommodating recess. At least a portion of the bonding element is disposed in the accommodating recess. The electronic unit is electrically connected to the conductive pad through the bonding element. The accommodating recess has a bottom surface and an opening opposite to the bottom surface, and a width of the bottom surface is greater than a width of the opening.

Abstract: A three-dimensional data encoding method includes: calculating coefficient values from pieces of attribute information of three-dimensional points included in point cloud data; quantizing the coefficient values individually to generate quantized values; and generating a bitstream including the quantized values. Each of the coefficient values belongs to any one of layers. In the quantizing, each of the coefficient values is quantized using a quantization parameter for a layer to which the coefficient value belongs among the layers, and the bitstream includes first information and pieces of second information, the first information indicating a reference quantization parameter, the pieces of second information being for calculating quantization parameters for the layers from the reference quantization parameter.

Abstract: A semiconductor device includes a first region and a second region, and the second region surrounds the first region. The semiconductor device includes at least one electronic unit, a redistribution structure, a plurality of first pads, and a plurality of second pads. The redistribution structure may be electrically connected to at least one electronic unit. A plurality of first pads are arranged on the redistribution structure and correspondingly to the first region. There is a first pitch between two adjacent first pads. A plurality of second pads are arranged on the redistribution structure and correspondingly to the second region. There is a second pitch between two adjacent second pads, so that the first pitch is smaller than the second pitch.

Abstract: A wafer processing system and a rework method thereof are provided. An image capture device captures an image of a wafer to generate a captured image. A control device detects a defect pattern in the captured image, calculates a target removal thickness according to distribution of contrast values of the defect pattern, and controls a processing device to perform processing on the wafer according to the target removal thickness.

Abstract: A three-dimensional data encoding method includes: obtaining geometry information which includes first three-dimensional positions on a measurement target, and is generated by a measurer that radially emits an electromagnetic wave in different directions and obtains a reflected wave which is the electromagnetic wave that is reflected by the measurement target; generating a two-dimensional image including first pixels corresponding to the directions, based on the geometry information; and encoding the two-dimensional image to generate a bitstream. Each of the first pixels has a pixel value indicating a first three-dimensional position or attribute information of a three-dimensional point which is included in a three-dimensional point cloud and corresponds to a direction to which the first pixel corresponds among the directions.

Abstract: A method of forming an image sensor includes forming a photodiode within a semiconductor substrate. The method further includes disposing an interconnect structure over the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL) over the photodiode; and a plurality of dielectric layers over the CESL, wherein at least one dielectric layer of the plurality of dielectric layers comprises a low dielectric constant (low-k) material. The method further includes patterning at least the plurality of dielectric layers, wherein patterning at least the plurality of dielectric layers comprises defining an opening above an active region of the photodiode. The method further includes depositing a cap layer on sidewalls of the opening, wherein the cap layer includes a dielectric material having a higher moisture resistance than the low-k dielectric material.

Abstract: The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a package structure, a circuit structure, a bonding structure and an external element. The circuit structure is disposed on the package structure and is electrically connected to the package structure. The circuit structure has a recess. The bonding structure includes a first bonding pad and a second bonding pad. The second bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad. The bonding structure is disposed between the circuit structure and the external element. The external element is electrically connected to the circuit structure through the bonding structure. A width of the first bonding pad is smaller than a width of the second bonding pad.

Abstract: An apparatus and method for efficiently generating clock signals. An integrated circuit includes multiple clock dividers both at its I/O boundaries and across its semiconductor die. A clock divider receives an input clock signal, and an indication of a reduction factor that is a positive, non-zero and a non-integer value less than one. The clock divider generates an output clock signal based on the input clock signal and the reduction factor. The reduction factor can be an M-bit pattern where M is a positive, non-zero integer greater than one. Therefore, the clock divider generates the output clock signal with a reduced clock rate that has a smallest configurable granularity that is 1/M of the input clock frequency. An asserted bit in the M-bit pattern indicates that the output clock signal should have an asserted value during a corresponding clock cycle of the input clock signal.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: An electronic device including an electronic unit and a redistribution layer is disclosed. The electronic unit has connection pads. The redistribution layer is electrically connected to the electronic unit and includes a first insulating layer, a first metal layer and a second insulating layer. The first insulating layer is disposed on the electronic unit and has first openings disposed corresponding to the connection pads. The first metal layer is disposed on the first insulating layer and electrically connected to the electronic unit through the connection pads. The second insulating layer is disposed on the first metal layer. The first insulating layer includes first filler particles, and the second insulating layer includes second filler particles. The first filler particles have a first maximum particle size, the second filler particles have a second maximum particle size, and the second maximum particle size is greater than the first maximum particle size.

Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.

Abstract: An electronic device and a related tiled electronic device are disclosed. The electronic device includes a protective layer, a circuit structure, a sensing element and a control unit. The circuit structure is disposed on the protective layer and surrounds the sensing element. The control unit is disposed between the circuit structure and the protective layer and electrically connected to the sensing element. The protective layer surrounds the control unit and contacts a surface of the circuit structure.

Abstract: A three-dimensional data encoding method includes: combining first point cloud data and second point cloud data to generate third point cloud data; and encoding the third point cloud data to generate encoded data. The encoded data includes identification information indicating whether each of three-dimensional points included in the third point cloud data belongs to the first point cloud data or the second point cloud data.

Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: A three-dimensional data encoding method includes encoding information of a current node included in an N-ary tree structure of three-dimensional points included in three-dimensional data, where N is an integer greater than or equal to 2. In the encoding, first information is encoded, the first information indicating a range for one or more referable neighboring nodes among neighboring nodes spatially neighboring the current node, and the current node is encoded with reference to a neighboring node within the range.