Patents by Inventor Chi Wang

Chi Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240313263
    Abstract: A lithium-ion battery includes a positive electrode, a negative electrode, and a non-aqueous electrolyte. The positive electrode includes a positive electrode material layer, the positive electrode material layer includes a positive electrode active material, and the positive electrode active material includes LiNixCoyMnzL(1-x-y-2)O2, where L is Al, Sr, Mg. Ti, Ca, Zr, Zn, Si, Cu, V or Fe, 0.5?x?1, 0?y?0.5, 0?z?0.5, 0?x+y+z?1, and an upper limit voltage of the lithium-ion battery is ?4.2 V. The non-aqueous electrolyte includes a solvent, an electrolyte salt and a compound represented by formula 1: A-D-B-E-C, Formula 1. Based on a total mass of the non-aqueous electrolyte as 100%, the compound represented by the formula 1 is added in an amount of 0.01 to 5.0%.
    Type: Application
    Filed: December 16, 2021
    Publication date: September 19, 2024
    Inventors: Shiguang Hu, Yunxian Qian, Chaowei Cao, Pengkai Guo, Xiaoxia Xiang, Chi Wang, Shuhuai Xiang, Qun Chen, Yonghong Deng
  • Publication number: 20240297279
    Abstract: A light source assembly is provided, including a substrate; a light-emitting element disposed on the substrate; and an optical film disposed on the light-emitting element. A diffuser layer is disposed between the optical film and the light-emitting element, wherein a haze of the diffuser layer is greater than 85%, a distance between the diffuser layer and the light-emitting element is in a range from 0 mm to 10 mm, and a thickness of the light-emitting element is less than the distance.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Inventors: Chia-Lun CHEN, Shih-Chang HUANG, Ming-Hui CHU, Chih-Chang CHEN, Kai-Hsien HSIUNG, Hui-Chi WANG, Wun-Yuan SU
  • Patent number: 12074252
    Abstract: An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure, a second type semiconductor structure, an active structure and a contact structure. The first type semiconductor structure is located on the substrate and has a first protrusion part with a first thickness and a platform part with a second thickness. The second type semiconductor structure is located on the first type semiconductor structure. The active structure is between the first type semiconductor structure and the second type semiconductor structure. The contact structure is disposed between the first type semiconductor structure and the substrate. The second thickness of the platform part is in a range of 0.01 ?m to 1 ?m.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: August 27, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chung-Hao Wang, Yu-Chi Wang, Yi-Ming Chen, Yi-Yang Chiu, Chun-Yu Lin
  • Patent number: 12066993
    Abstract: The present disclosure relates to systems, methods, and computer-readable media for determining optimal index configurations for processing workloads in a database management system. For instance, an index configuration system can efficiently determine a subset of indexes for processing a workload utilizing one or more reinforcement learning models. For example, in various implementations, the index configuration system utilizes a Markov decision process and/or a Monte Carlo tree search model to determine an optimal subset of indexes for processing a workload in a manner that effectively utilizes computing device resources while also avoiding significant interference with customer workloads.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: August 20, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Wentao Wu, Chi Wang, Tarique Ashraf Siddiqui, Vivek Ravindranath Narasayya, Surajit Chaudhuri
  • Publication number: 20240273773
    Abstract: A three-dimensional data encoding method includes generating a bitstream by encoding subspaces included in a current space including three-dimensional points. In the generating of the bitstream: first information is stored in a first header which is common to the subspaces and included in the bitstream, the first information indicating first coordinates which are coordinates of the current space; and second information is stored in a second header which is provided on a subspace basis and included in the bitstream, the second information indicating a difference between second coordinates which are coordinates of a corresponding subspace among the subspaces and the first coordinates.
    Type: Application
    Filed: April 16, 2024
    Publication date: August 15, 2024
    Inventors: Chung Dean HAN, Pongsak LASANG, Chi WANG, Toshiyasu SUGIO
  • Publication number: 20240267541
    Abstract: The present invention provides an encoder including a quantization circuit, a control circuit and an encoding circuit is disclosed. The quantization circuit is configured to generate quantized data corresponding to a CTU according to image data, wherein the CTU comprises at least one TU. The control circuit is configured to determine a number of allocated bits for each TU in the CTU, where the number of allocated bits for each TU is determined based on a sum of remaining bits of the TUs that have been encoded. The encoding circuit is configured to encode each TU to obtain encoded data according to the number of allocated bits of the TU in the CTU.
    Type: Application
    Filed: February 8, 2023
    Publication date: August 8, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Weimin Zeng, Chi-Wang Chai, Wei Pu, Wujun Chen, Wei Li
  • Publication number: 20240267528
    Abstract: The present invention provides an encoder including a quantization circuit, an encoding circuit, an energy parameter calculation circuit and a quantization parameter determination circuit. The quantization circuit is configured to perform quantization operations on a plurality of CTUs in image data in sequence to generate quantized data respectively corresponding to the plurality of CTUs. The encoding circuit is configured to perform encoding operations on the quantized data of the plurality of CTUs in sequence to generate encoded data. The energy parameter calculation circuit is configured to receive the image data, and calculate a plurality of energy parameters respectively corresponding to the plurality of CTUs in the image data. The quantization parameter determination circuit is configured to determine a plurality of quantization parameters of the plurality of CTUs according to at least a portion of the plurality of energy parameters, for the quantization circuit to perform the quantization operations.
    Type: Application
    Filed: February 8, 2023
    Publication date: August 8, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, Wujun Chen, Wei Pu
  • Patent number: 12057467
    Abstract: A method includes forming a plurality of openings extending into a substrate from a front surface of the substrate. The substrate includes a first semiconductor material. Each of the plurality of openings has a curve-based bottom surface. The method includes filling the plurality of openings with a second semiconductor material. The second semiconductor material is different from the first semiconductor material. The method includes forming a plurality of pixels that are configured to sense light in the plurality of openings, respectively, using the second semiconductor material.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yeh-Hsun Fang, Chiao-Chi Wang, Chung-Chuan Tseng, Chia-Ping Lai
  • Publication number: 20240258218
    Abstract: A semiconductor package device is provided. The semiconductor package device includes a circuit substrate having a first terminal end; a chip disposed on the circuit substrate and having a conductive pad; an auxiliary structure disposed between the first terminal end and the conductive pad, wherein the chip is electrically connected to the circuit substrate through the auxiliary structure; and a protective layer disposed on the circuit substrate and surrounding the chip, wherein the width of the first terminal end is greater than or equal to the width of the auxiliary structure.
    Type: Application
    Filed: January 3, 2024
    Publication date: August 1, 2024
    Inventors: Cheng-Chi WANG, Kuan-Hsueh LIN, Shih-Kang LIN
  • Publication number: 20240258241
    Abstract: The present disclosure provides an electronic device and a manufacturing method. The electronic device includes a base layer, a first redistribution structure, a first electronic unit, a second electronic unit, a protecting layer, and a connecting component. The base layer includes at least one via structure. The first redistribution structure is disposed on the base layer, and the first electronic unit and the second electronic unit are disposed on the first redistribution structure. The protecting layer surrounds the first electronic unit and the second electronic unit, and the first electronic unit and the second electronic unit are electrically connected to the connecting component through the first redistribution structure and the at least one via structure.
    Type: Application
    Filed: January 7, 2024
    Publication date: August 1, 2024
    Applicant: InnoLux Corporation
    Inventors: Jui-Jen YUEH, Cheng-Chi Wang, Ju-Li Wang
  • Publication number: 20240259577
    Abstract: The present invention provides a receiver including a decoder, an upscale circuit and a color space conversion circuit. The decoder is configured to decode a video stream to generate a base layer and an enhancement layer. The upscale circuit is configured to perform an upscaling operation on the base layer to generate an upscaled base layer, wherein the upscaled base layer comprises luminance values of a plurality of pixels of a frame, and the enhancement layer comprises residuals of the plurality of pixels of the frame. The color space conversion circuit is configured to use a conversion matrix to combine the upscaled base layer and the enhancement layer to generate output video data.
    Type: Application
    Filed: February 1, 2023
    Publication date: August 1, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventor: Chi-Wang Chai
  • Publication number: 20240255714
    Abstract: The present disclosure provides a semiconductor device, including a substrate structure, a photonic unit, an optical fiber and a chip unit. The substrate structure includes a coupling member. The photonic unit is disposed in a first recess of the coupling member. The optical fiber is disposed in a second recess of the coupling member and optically coupled to the photonic unit. The chip unit is disposed on the substrate structure and electrically connected to the photonic unit through the coupling member. A depth of the second recess is greater than or equal to half a diameter of the optical fiber.
    Type: Application
    Filed: January 10, 2024
    Publication date: August 1, 2024
    Applicant: InnoLux Corporation
    Inventors: Cheng-Chi WANG, Jui-Jen YUEH
  • Patent number: 12044631
    Abstract: A wafer surface defect inspection method and a wafer surface defect inspection apparatus are provided. The method includes the following steps. Scanning information of a wafer is received, and the scanning information includes multiple scanning parameters. At least one reference point of the scanning information is determined, and path information is generated according to the at least one reference point and a reference value. Multiple first scanning parameters corresponding to the path information in the scanning parameters are obtained according to the path information to generate a curve chart. According to the curve chart, it is determined whether the wafer has a defect, and a defect type of the defect is determined.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: July 23, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Shang-Chi Wang, Miao-Pei Chen, Han-Zong Wu, Chia-Chi Tsai, I-Ching Li
  • Patent number: 12046640
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: July 23, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 12046639
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: July 23, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 12047038
    Abstract: A reconfigurable crystal oscillator and a method for reconfiguring a crystal oscillator are provided. The reconfigurable crystal oscillator includes a transconductance circuit, a feedback resistor, a crystal tank, an input-end capacitor and an output-end capacitor. Both of the feedback resistor and the crystal tank are coupled between an input terminal and an output terminal of the transconductance circuit. The input-end capacitor is coupled to the input terminal of the transconductance circuit, and the output-end capacitor is coupled to the output terminal of the transconductance circuit. In particular, the transconductance circuit is configured to provide a transconductance, and when an operation mode of the reconfigurable crystal oscillator is switched, an input-end capacitance of the input-end capacitor and an output-end capacitance of the output-end capacitor are switched, respectively.
    Type: Grant
    Filed: December 25, 2022
    Date of Patent: July 23, 2024
    Assignee: MEDIATEK INC.
    Inventors: Keng-Meng Chang, Sen-You Liu, Yao-Chi Wang
  • Publication number: 20240243108
    Abstract: An electronic device is provided. The electronic device includes a substrate, a plurality of light-emitting elements, and a protective layer. The substrate includes a connecting element. The plurality of light-emitting elements is disposed on the substrate. The protective layer is disposed on the substrate and includes an opaque layer and a transparent layer. The opaque layer has a plurality of openings. At least a portion of the transparent layer is disposed in the openings and covers the respective light-emitting elements. The protective layer surrounds the connecting element.
    Type: Application
    Filed: January 2, 2024
    Publication date: July 18, 2024
    Inventors: Jui-Jen YUEH, Kuan-Feng LEE, Jia-Yuan CHEN, Cheng-Chi WANG
  • Publication number: 20240244179
    Abstract: A three-dimensional data encoding method includes: encoding a first flag indicating whether a node having a parent node different from a parent node of a current node is to be referred to in encoding of the current node included in an n-ary tree structure of three-dimensional points included in three-dimensional data; selecting a coding table from N coding tables according to occupancy states of neighboring nodes of the current node, and performing arithmetic encoding on information of the current node using the coding table selected, when the first flag indicates that the node is to be referred to; and selecting a coding table from M coding tables according to the occupancy states of the neighboring nodes of the current node, and performing arithmetic encoding on information of the current node using the coding table selected, when the first flag indicates that the node is not to be referred to.
    Type: Application
    Filed: February 15, 2024
    Publication date: July 18, 2024
    Inventors: Toshiyasu SUGIO, Chi Wang, Pongsak LASANG, Chung Dean HAN, Noritaka IGUCHI
  • Patent number: 12033363
    Abstract: A three-dimensional data encoding method includes: encoding first information of a first current node or second information of a second current node, the first current node being included in an N-ary tree structure of first three-dimensional points included in a first three-dimensional point cloud, N being 2 or 4, the second current node being included in an octree structure of second three-dimensional points included in a second three-dimensional point cloud The encoding of the first information or the second information includes encoding the first information using a first encoding pattern including a pattern common to a second encoding pattern used in encoding the second information.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: July 9, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Toshiyasu Sugio, Noritaka Iguchi, Chi Wang, Pongsak Lasang, Chung Dean Han
  • Publication number: 20240218294
    Abstract: A cleaning composition for electronics industries is provided. The cleaning composition includes 40% to 90% by weight of an amine solvent having a structure of following formula (1), a quaternary ammonium salt, and water. Wherein, R1, R2, R4, and R5 are each independently hydrogen, a linear alkyl group having 1 to 4 carbon atoms, a branched alkyl group having 3 to 5 carbon atoms, a linear alkylamine having 1 to 4 carbon atoms, or a branched alkylamine having 3 to 5 carbon atoms, and R3 is a linear alkylene group having 1 to 5 carbon atoms or a branched alkylene group having 3 to 5 carbon atoms.
    Type: Application
    Filed: November 6, 2023
    Publication date: July 4, 2024
    Applicant: Daxin materials corporation
    Inventors: Hui-yi TANG, Tzu-chi WANG, Yi-cheng CHEN