Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.

Abstract: A display system is provided, which may include a processor, a controller, a video combiner and a display panel. The controller receives a first input signal and a second input signal, generates a first control instruction and a second control instruction according to the first input signal and the second input signal respectively, and generates a first video data, a second video data, and a plurality of timing signals respectively according to the first control instruction and the second control instruction. The video combiner combines the first video data with the second video data to generate a combined video data. The display panel displays the combined video data according to the timing signals.

Abstract: A dye kit comprising: (A) a dyeing composition (A) and (B) a pyrazolone composition (B) comprising a retarding combination of pyrazolone compound and a reducer.

Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.

Abstract: A method of manufacturing a semiconductor structure includes providing a substrate including a redistribution layer (RDL) disposed over the substrate, disposing a first patterned mask over the RDL, disposing a first conductive material over the RDL exposed from the first patterned mask to form a first conductive pillar, removing the first patterned mask, disposing a second patterned mask over the RDL, disposing a second conductive material over the RDL exposed from the second patterned mask to form a second conductive pillar, removing the second patterned mask, disposing a first die over the first conductive pillar, and disposing a second die over the second conductive pillar. A height of the second conductive pillar is substantially greater than a height of the first conductive pillar.

Abstract: A receiver circuit has a first stage circuit having a first stage input and a first stage output, the first stage output setting a first stage common mode voltage; a second stage circuit having a second stage input connected to the first stage output, and a second stage output setting a second stage common mode voltage; and a buffer circuit having a trip point voltage, connected to the second stage output. The first stage circuit can include circuit elements configured to establish the first stage common mode voltage so that the second stage common mode voltage matches the trip point voltage. The second stage circuit can include a self-biased amplifier.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first under-bump metallization (UBM) pattern, a first conductive via, and a first dielectric layer laterally covering the first UBM pattern and the first conductive via. Entireties of a top surface and a bottom surface of the first UBM pattern are substantially planar. The first conductive via landing on the top surface of the first UBM pattern includes a vertical sidewall and a top surface connected to the vertical sidewall, and a planarized mark is on the top surface of the first conductive via. A bottom surface of the first dielectric layer is substantially flush with the bottom surface of the first UBM, and a top surface of the first dielectric layer is substantially flush with the top surface of the first conductive via.

Abstract: A micro light emitting diode display device includes a light-transmissive unit, a plurality of light emitting units and a plurality of converting units. The light-transmissive unit includes a protective layer which has opposite first and second surfaces. The light emitting units are arranged in an array on the second surface of the protective layer and each of the light emitting units includes first, second and third light emitting portions. The converting units are disposed on the first surface of the protective layer in positions corresponding to the light emitting units, respectively, and each of the converting units includes a reflecting feature, and first and second wavelength converting elements.

Abstract: A power management system and method including: determining a maximum power function with respect to a computing node; determining a power cap value, wherein the power cap value is the greater of the maximum power function and a minimum power consumption value of the computing node; and allocating the power cap value to the computing node, wherein the maximum power function is a product of a total power and a power ratio of the computing node.

Abstract: Systems, methods, circuits, and apparatus for managing flip flop circuits are provided. In one aspect, a flip flop circuit includes a first sub-circuit having a first inner node between a first input node and a first output node, a second sub-circuit having a second inner node between a second input node and a second output node, and a third sub-circuit coupled between the first and second inner nodes. The third sub-circuit is configured to be: in an open state to conductively disconnect the first and second inner nodes, and in a close state to conductively connect the first and second inner nodes, such that a first output at the first output node corresponds to a second input at the second input node and a second output at the second output node corresponds to a first input at the first input node.

Abstract: Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a workpiece, the workpiece including a second die. The workpiece is mounted to a front side of a package substrate, where the first die is at least partially disposed in a through hole in the package substrate. A heat dissipation feature may be attached on a second side of the workpiece. An encapsulant may be formed on the front side of the package substrate around the workpiece.

Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.

Abstract: Respiratory systems with a flow generator can provide bubble CPAP therapy by controlling the pressure of a flow of gas delivered to a patient. The controller of the respiratory system can control a motor speed of its flow generator so as to control the pressure of the flow of gas. The controller can also detect presence of bubbling and/or possible leaks in the gas pathway of the system. The respiratory system can include a high flow respiratory system.

Abstract: Enclosure assemblies with integrating flashing for protecting an accessory on a rooftop. The enclosure assemblies can include a base configured to protect the rooftop from water intrusion and a cover configured to be joined to the raised portion of the base. The base can include a bottom wall and a raised portion extending from the bottom wall. The base can include an uphill portion configured to be positioned beneath at least one full course of roof shingle on the rooftop, without having to cut the roof shingle. The raised portion can be disposed off-center relative to the central transverse axis of the bottom wall, leaving the uphill portion of the bottom wall uncovered.

Abstract: Disclosed is an adjustable cryoablation needle, comprising a needle rod (3), a front-segment heat-insulated tube (1), a rear-segment heat-insulated tube (2), and an gas inlet structure (7) penetrating the needle rod (3) and the front-segment heat-insulated tube (1), wherein the needle rod (3) can move relative to the rear-segment heat-insulated tube (2) in the axial direction of the rear-segment heat-insulated tube (2) so as to adjust a first axial distance between the front end of the rear-segment heat-insulated tube (2) and the front end of the needle rod (3); and the front-segment heat-insulated tube (1) can move relative to the rear-segment heat-insulated tube (2) in the axial direction of the rear-segment heat-insulated tube (2) The adjustable cryoablation needle can prevent the inconvenience caused by a doctor selecting the model of the cryoablation needle.

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for managing bit line voltage generating circuits in memory devices are provided. An example bit line voltage generating circuit is configured to provide a stable clamping voltage to at least one bit line connecting memory cells in the memory device. The bit line voltage generating circuit includes an operational amplifier configured to receive a reference voltage, a feedback voltage, and a compensation current and output an output voltage, and an output transistor configured to provide a terminal voltage as the feedback voltage and the output voltage as a target voltage that is associated with the clamping voltage.

Abstract: An item with fibers may be picked up and placed using a tool head with hooks that engage the fibers. The tool head may comprise at least one hook portion and at least one contact surface adjacent to the hook portion. The hooks that engage the fibers may extend from the hook portion. The tool head may be actuatable between at least a first configuration that permits the hooks to engage the fibers and a second configuration that does not permit the hooks to engage the fibers. An item may be picked up at a starting location with a tool head in the first configuration and placed at a placement location by moving the tool head and then actuating the tool head to the second configuration.

Abstract: A light source for EUV is provided. The light source includes a target droplet generator, a laser generator, and a controller. The target droplet generator is configured to provide target droplets to a source vessel. The laser generator is configured to provide first laser pulses according to a control signal to irradiate the target droplets in the source vessel. The controller is configured to provide the control signal according to at least two of process parameters including temperature of the source vessel, droplet positions of the target droplets, and beam sizes and focal points of the first laser pulses. When the average value or the standard deviation of the temperature of the source vessel and the droplet positions of the target droplets exceed the predetermined range, the controller is configured to provide the control signal to the laser generator to stop providing the first laser pulses.

Abstract: The present invention provides a method for manufacturing an epitaxial film and the epitaxial film thereof. The method comprises the steps of: providing a first single crystal substrate and forming a sacrificial layer and a first epitaxial film on the first single crystal substrate; removing the sacrificial layer in order to separate the first epitaxial film from the first single crystal substrate; shifting the first epitaxial film to a second single crystal substrate so as to let the first epitaxial film cover on a partial surface of the second single crystal substrate, wherein the first epitaxial film and the second single crystal substrate are two different crystallographic plane orientations in absolute coordinates; and forming a second epitaxial film on the first epitaxial film and the second single crystal substrate, so as to let the second epitaxial film has at least two crystallographic plane orientations.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first under-bump metallization (UBM) pattern covered by a first dielectric layer, and the first UBM pattern includes a surface substantially leveled with a surface of the first dielectric layer. The circuit substrate is electrically coupled to the redistribution structure through a conductive joint disposed on the surface of the first UBM pattern. The insulating encapsulation is disposed on the redistribution structure to cover the circuit substrate.