Patents by Inventor Chia-Cheng Chang

Chia-Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210057290
    Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Shiang LIN, Chia-Cheng HO, Chun-Chieh LU, Cheng-Yi PENG, Chih-Sheng CHANG
  • Patent number: 10930701
    Abstract: A light-emitting device includes a first semiconductor layer having an uppermost surface and a bottommost surface; a first light-emitting structure and a second light-emitting structure formed on the same first semiconductor layer, wherein the first semiconductor layer is continuous; a first trench formed between the first and the second light-emitting structures; and a second electrode formed on the second semiconductor layer and including a second pad and a plurality of second extending parts extending from the second pad; wherein the second pad is between the first and the second light-emitting structures, and the plurality of second extending parts extends to the first and the second light-emitting structures, respectively; wherein the first trench passes through the uppermost surface but does not extend to the bottommost surface; wherein the first trench includes an equal width in a top view.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: February 23, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Chen Ou, Chun-Wei Chang, Chih-Wei Wu, Sheng-Chih Wang, Hsin-Mei Tsai, Chia-Chen Tsai, Chuan-Cheng Chang
  • Publication number: 20210025831
    Abstract: A lid detecting system includes a first lid screwing device, a second lid screwing device, a scanning device and a removing device. The first lid screwing device is configured for positioning a lid of a container on a body of the container and rotationally tightening the lid of the container to the body of the container by a pre-screwing torque. The second lid screwing device is configured for rotationally tightening the lid of the container to the body of the container by a screwing torque. The scanning device is disposed between the first lid screwing device and the second lid screwing device and configured for scanning a top surface of the lid of the container so as to obtain a detecting value. The removing device is configured for removing the container when the detecting value is greater than a predetermined value.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 28, 2021
    Inventors: Chi-Huan SHIH, Chia-Kai CHANG, Chang-Cheng CHEN
  • Patent number: 10903198
    Abstract: A semiconductor package assembly and method for forming the same are provided. The semiconductor package assembly includes a first semiconductor die and a second semiconductor die disposed on a first surface of a substrate. The first semiconductor die includes a peripheral region having a second edge facing the first edge of the second semiconductor die and a third edge opposite to the second edge, a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: January 26, 2021
    Assignee: MEDIATEK INC
    Inventors: Chia-Cheng Chang, I-Hsuan Peng, Tzu-Hung Lin
  • Publication number: 20210012481
    Abstract: A method of counting sheet materials applied to a pile of sheet materials, comprising the steps of: receiving an image of the pile of sheet materials; obtaining a grayscale value of a plurality of pixels along a first image axis direction of the image to form an one dimensional first array; performing binarization of the first elements of the first array with a first threshold value to form an one dimensional second array; obtaining the number of the second elements of a first value appearing between two second elements of a second value in the second array to form a third array; dividing the elements of the third array into a first cluster and a second cluster with a second threshold value; counting the number of the third elements belonging to the first cluster and defining said number as the number of the first sheet materials.
    Type: Application
    Filed: June 23, 2020
    Publication date: January 14, 2021
    Applicant: GLOBALWAFERS CO., LTD.
    Inventors: WEI-CHENG CHANG, CHIA-YEH LEE, HAN-ZONG WU
  • Patent number: 10879119
    Abstract: In a method of manufacturing a semiconductor device, initial connection patterns are prepared, initial cutting patterns for cutting the initial connection patterns are prepared, non-functional connection patterns at least from the initial connection patterns are identified, final cutting patterns are prepared from the initial cutting patterns and the non-functional connection patterns, a photo mask is prepared from the final cutting patterns, a photo resist pattern is formed over a target layer by a lithography operation using the photo mask, the target layer is patterned to form openings in the target layer by using the photo resist pattern, and connection layers are formed by filling the openings with a conductive material.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yuan-Yen Lo, Chia-Cheng Chang, Ming-Jhih Kuo, Chien-Yuan Chen
  • Patent number: 10879061
    Abstract: Semiconductor devices and a method for forming the same are provided. In various embodiments, a method for forming a semiconductor device includes receiving a semiconductor substrate including a channel. An atmosphere-modulation layer is formed over the channel. An annealing process is performed to form an interfacial layer between the channel and the atmosphere-modulation layer.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chun-Heng Chen, Hong-Fa Luan, Xiong-Fei Yu, Hui-Cheng Chang, Chia-Wei Hsu
  • Publication number: 20200403091
    Abstract: A gate-sinking pseudomorphic high electron mobility transistor comprises a compound semiconductor substrate overlaid with an epitaxial structure which includes sequentially a buffer layer, a channel layer, a Schottky layer, and a first cap layer. The Schottky layer comprises from bottom to top at least two stacked regions of semiconductor material. Each of the two adjacent stacked regions differs in material from the other and provides a stacked region contact interface therebetween. In any two adjacent stacked regions of the Schottky layer, one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material. A gate-sinking region is beneath the first gate metal layer of the gate electrode, and the bottom boundary of the gate-sinking region is located at the one of the at least one stacked region contact interface of the Schottky layer.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Inventors: Chia-Ming CHANG, Jung-Tao CHUNG, Chang-Hwang HUA, Ju-Hsien LIN, Yan-Cheng LIN, Yu-Chi WANG
  • Publication number: 20200391033
    Abstract: The invention relates to an electrochemical dephosphorylation technique for treating Alzheimer's disease and a use thereof. It comprises a gold electrode provided with a negative potential of ?0.2 V to ?0.6 V on a surface thereof.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Inventors: JUNG-CHIH CHEN, I-CHIU LI, KUN-CHE LI, CHING-CHENG CHUANG, MEI-LAN KO, HSIN-YU CHEN, CHIA-HSUAN CHANG, HSIN-YI TSAI, CHIEN-CHIH HSU
  • Publication number: 20200388706
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang CHEN, Chih-Ming LAI, Ching-Wei TSAI, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kuo-Cheng CHIANG, Ru-Gun LIU, Wei-Hao WU, Yi-Hsiung LIN, Chia-Hao CHANG, Lei-Chun CHOU
  • Publication number: 20200381425
    Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Inventors: Chia-Ming CHANG, Jung-Tao CHUNG, Yan-Cheng LIN, Lung-Yi TSENG
  • Patent number: 10852795
    Abstract: A method for system power management includes steps of detecting power output of plural power-supplying units (PSUs) and power consumption of plural computing node, so as to indirectly obtain real-time auxiliary power consumption of an auxiliary unit and continuously update maximum auxiliary power consumption; when one of the PSUs is malfunctioned, renewing the maximum sum of the power output of the other PSUs, and applying the difference of the renewed maximum sum of the power outputs and the maximum auxiliary power consumption as a first sum of the node power consumptions of the computing nodes; finally, according to the first sum of the node power consumptions, cutting down the power consumption of at least one of the computing nodes to a first node power consumption.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: December 1, 2020
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Wei-Cheng Wang, Chia-Cheng Chang
  • Publication number: 20200365526
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto, wherein the substrate includes a wiring structure, and a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The package further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are separated by a molding material. A first hole and a second hole are formed on the second surface of the substrate. Finally, a frame is disposed over the first surface of the substrate, wherein the frame surrounds the first semiconductor die and the second semiconductor die.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Tzu-Hung LIN, Chia-Cheng CHANG, I-Hsuan PENG, Nai-Wei LIU
  • Patent number: 10840134
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-yi Ruan
  • Patent number: 10825229
    Abstract: A projection-based frame is generated according to an omnidirectional video frame and a triangle-based projection layout. The projection-based frame has a 360-degree image content represented by triangular projection faces assembled in the triangle-based projection layout. A 360-degree image content of a viewing sphere is mapped onto the triangular projection faces via a triangle-based projection of the viewing sphere. One side of a first triangular projection face has contact with one side of a second triangular projection face, one side of a third triangular projection face has contact with another side of the second triangular projection face. One image content continuity boundary exists between one side of the first triangular projection face and one side of the second triangular projection face, and another image content continuity boundary exists between one side of the third triangular projection face and another side of the second triangular projection face.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 3, 2020
    Assignee: MEDIATEK INC.
    Inventors: Jian-Liang Lin, Hung-Chih Lin, Chia-Ying Li, Shen-Kai Chang, Chi-Cheng Ju, Chao-Chih Huang, Hui Ouyang
  • Publication number: 20200343357
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Application
    Filed: July 8, 2020
    Publication date: October 29, 2020
    Inventors: Po-Chi Wu, Chia-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: D902981
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao
  • Patent number: D902982
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao
  • Patent number: D908775
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 26, 2021
    Assignee: TDK Taiwan Corp.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao
  • Patent number: D909383
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: February 2, 2021
    Assignee: Trimble Inc.
    Inventors: Michael George Sanders, Jonathan Musch, Gerald Steiger, Katherine Allen, Mathias Roehring, Karl Forsberg, Markus Stridsberg, Niklas Briheim, Jungha Lee, Chen-Cheng Su, Chia Hung Wu, Yu Juei Chang