Patents by Inventor Chia-Cheng Chang

Chia-Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11374136
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20220199756
    Abstract: Metal insulator metal capacitors or backend transistors having epitaxial oxides are described. In a first example, metal-insulator-metal (MIM) capacitor includes a first electrode plate. A capacitor dielectric is on the first electrode plate. The capacitor dielectric includes a single crystalline oxide material. A second electrode plate is on the capacitor dielectric, the second electrode plate having a portion over and parallel with the first electrode plate. In a second example, a transistor includes a gate electrode above a substrate. A gate dielectric above and on the gate electrode. The gate dielectric includes a single crystalline oxide material. A channel material layer is on the single crystalline oxide material. Source or drain contacts are on the channel material layer.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Inventors: I-Cheng TUNG, Kaan OGUZ, Chia-Ching LIN, Sou-Chi CHANG, Matthew V. METZ, Uygar E. AVCI
  • Publication number: 20220199758
    Abstract: Capacitors with a carbon-based electrode layer in contact with a ferroelectric insulator. The insulator may be a perovskite oxide. Low reactivity of the carbon-based electrode may improve stability of a ferroelectric capacitor. A carbon-based electrode layer may be predominantly carbon and have a low electrical resistivity. A carbon-based electrode layer may be the only layer of an electrode, or it may be a barrier between the insulator and another electrode layer. Both electrodes of a capacitor may include a carbon-based electrode layer, or a carbon-based electrode layer may be included in only one electrode.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Arnab Sen Gupta, Jason C. Retasket, Matthew V. Metz, I-Cheng Tung, Chia-Ching Lin, Sou-Chi Chang, Kaan Oguz, Uygar E. Avci, Edward Johnson
  • Publication number: 20220199519
    Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. The first capacitor dielectric is or includes a perovskite high-k dielectric material. A second electrode plate is on the first capacitor dielectric and has a portion over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and has a portion over and parallel with the second electrode plate.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: Chia-Ching LIN, Sou-Chi CHANG, Kaan OGUZ, I-Cheng TUNG, Arnab SEN GUPTA, Ian A. YOUNG, Uygar E. AVCI, Matthew V. METZ, Ashish Verma PENUMATCHA, Anandi ROY
  • Patent number: 11358177
    Abstract: This invention discloses a system and method for detecting a cover with an abnormal condition. The system includes a transport track for defining a sliding direction of at least one cover with a detection surface. The transport track has a detection area and a cover removal area, and includes a pair of bottom rails and a pair of side rails. The pair of bottom rails support the cover at an inclination angle so that the cover slides on the pair of bottom rails. The cover is located between the pair of side rails, and the sliding direction of the cover is defined by the pair of side rails. The detection area is used for detecting the detection surface of the cover, and the cover removal area has an outlet for removing a cover with an abnormal condition determined based on a detection result of the detection surface thereof.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: June 14, 2022
    Assignee: CVC TECHNOLOGIES, INC.
    Inventors: Chi-Huan Shih, Chia Kai Chang, Chang Cheng Chen
  • Publication number: 20220181433
    Abstract: Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.
    Type: Application
    Filed: December 9, 2020
    Publication date: June 9, 2022
    Applicant: Intel Corporation
    Inventors: Sou-Chi Chang, Chia-Ching Lin, Kaan Oguz, I-Cheng Tung, Uygar E. Avci, Matthew V. Metz, Ashish Verma Penumatcha, Ian A. Young, Arnab Sen Gupta
  • Publication number: 20220180007
    Abstract: Examples of of centralized access control of an input-output (I/O) resource of a computing device are described herein. In an example, access rights available for a user for the I/O resource are determined based on user identification data, and access to the I/O resource to the user is controlled centrally based on the available access rights associated with the user.
    Type: Application
    Filed: August 26, 2019
    Publication date: June 9, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Tsue-Yi Huang, Chia-Cheng Lin, Heng-Fu Chang, Nung-Kai Chen
  • Publication number: 20220173104
    Abstract: A semiconductor device includes first and second fins, first and second hafnium oxide layers, first and second cap layers, and first and second metal gate electrodes. The first and second fins protrude above a substrate and respectively have an n-channel region and a p-channel region. The first and second hafnium oxide layers wrap around the n-channel region and the p-channel region, respectively. The first and second cap layers wrap around the first and second annular hafnium oxide layers, respectively. The first and second cap layers are made of a same material that is lanthanum oxide, yttrium oxide, or strontium oxide. The first and second metal gate electrodes wrap around the first and second cap layers, respectively. The first and second metal gate electrodes have a same metal composition. The first and second gate dielectrics have a same dielectric composition.
    Type: Application
    Filed: February 18, 2022
    Publication date: June 2, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yuan CHANG, Xiong-Fei YU, Hui-Cheng CHANG
  • Publication number: 20220171688
    Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.
    Type: Application
    Filed: February 18, 2022
    Publication date: June 2, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hung CHANG, Atul KATOCH, Chia-En HUANG, Ching-Wei WU, Donald G. MIKAN, JR., Hao-I YANG, Kao-Cheng LIN, Ming-Chien TSAI, Saman M.I. ADHAM, Tsung-Yung CHANG, Uppu Sharath CHANDRA
  • Patent number: 11349247
    Abstract: An electrical plug connector includes a metallic shell and first and second insulated housings in the metallic shell. An insertion cavity is between an inner side of an assembly of the first insulated housing and the second insulated housing. The first terminals, from right to left, include a rightmost first ground terminal, a pair of first high-speed signal terminals, a first power terminal, a first function detection terminal, a pair of first low-speed signal terminals, and a leftmost first ground terminal. First flexible contact portions of the first terminals are in the insertion cavity. The second terminals, from right to left, include a second power terminal, a pair of second high-speed signal terminals, and a second power terminal. Second flexible contact portions of the second terminals are in the insertion cavity.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: May 31, 2022
    Assignee: ADVANCED-CONNECTEK INC.
    Inventors: Ming-Yung Chang, Tzu-Hao Li, Chia-Cheng He
  • Publication number: 20220162750
    Abstract: A powder atomic layer deposition apparatus with special cover lid is disclosed, which includes a vacuum chamber, a shaft sealing device, and a driving unit that drives the vacuum chamber to rotate through the shaft sealing device. The vacuum chamber includes a chamber and a cover lid having an inner surface. At least one fan unit and a monitor wafer are arranged on the inner surface of the cover lid, wherein the monitor wafer is located between the fan unit and the cover lid, and there is a gap between the monitor wafer and the fan unit. An air intake line directs a gas toward the fan unit, and the fan unit drives the gas to flow throughout a reaction space, so that powders in the reaction space are blown around for thin films of uniform thickness to form on the surface of the powders and the monitor wafer.
    Type: Application
    Filed: May 30, 2021
    Publication date: May 26, 2022
    Inventors: JING-CHENG LIN, JUNG-HUA CHANG, CHIA-CHENG KU
  • Publication number: 20220148938
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 12, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng LIN, Cheng-Wei CHOU, Ting-En HSIEH, Yi-Han HUANG, Kwang-Ming LIN, Yung-Fong LIN, Cheng-Tao CHOU, Chi-Fu LEE, Chia-Lin CHEN, Shu-Wen CHANG
  • Publication number: 20220139848
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die disposed over the substrate, and a frame disposed over the substrate. The frame is adjacent to the semiconductor die, and an upper surface of the frame is lower than the upper surface of the semiconductor die. IN addition, a passive component is disposed on the substrate and located between the frame and the semiconductor die.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Inventors: Chia-Cheng CHANG, Tzu-Hung LIN, I-Hsuan PENG, Yi-Jou LIN
  • Patent number: 11307643
    Abstract: A power management system includes connection interfaces, a system power supply, and a power management circuit. Each connection interface is connected to one power consumption device. The system power supply includes power supply units (PSUs). The system power supply supplies electricity power to each power consumption device via one connection interface. The power management circuit is connected to each power consumption device via the connection interfaces. The power management circuit obtains a current total load of PSUs, determines a target load of each PSU, and determines whether each connection interface is connected to one power consumption device. The power management circuit turns off power supply to the connection interface that is not connected to the power consumption devices. According to the current total load and the target load, the power management circuit determines an enabled number of the PSUs, thereby turning on or turning off each PSU accordingly.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: April 19, 2022
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Wei-Cheng Wang, Chia-Neng Yang, Chia-Cheng Chang
  • Patent number: 11264337
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die and a frame. The semiconductor die is disposed over the substrate. The frame is disposed over the substrate, wherein the frame is adjacent to the semiconductor die, and the upper surface of the frame is lower than the upper surface of the semiconductor die.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: March 1, 2022
    Assignee: MEDIATEK INC.
    Inventors: Chia-Cheng Chang, Tzu-Hung Lin, I-Hsuan Peng, Yi-Jou Lin
  • Publication number: 20220020726
    Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.
    Type: Application
    Filed: September 29, 2021
    Publication date: January 20, 2022
    Inventors: Chia-Cheng CHANG, Tzu-Hung LIN, I-Hsuan PENG, Yi-Jou LIN
  • Patent number: 11171113
    Abstract: A semiconductor package structure includes a substrate having a first surface and second surface opposite thereto, a first semiconductor die disposed on the first surface of the substrate, a second semiconductor die disposed on the first surface, a molding material surrounding the first semiconductor die and the second semiconductor die, and an annular frame mounted on the first surface of the substrate. The first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. The first semiconductor die is separated from the second semiconductor die by the molding material. The substrate includes a wiring structure. The first semiconductor die and the second semiconductor die are electrically coupled to the wiring structure. The annular frame surrounds the first semiconductor die and the second semiconductor die. The annular frame includes a retracted region at an outer corner of the annular frame.
    Type: Grant
    Filed: September 8, 2019
    Date of Patent: November 9, 2021
    Assignee: MEDIATEK INC.
    Inventors: Chia-Cheng Chang, Tzu-Hung Lin, I-Hsuan Peng, Yi-Jou Lin
  • Publication number: 20210303059
    Abstract: A power management system includes connection interfaces, a system power supply, and a power management circuit. Each connection interface is connected to one power consumption device. The system power supply includes power supply units (PSUs). The system power supply supplies electricity power to each power consumption device via one connection interface. The power management circuit is connected to each power consumption device via the connection interfaces. The power management circuit obtains a current total load of PSUs, determines a target load of each PSU, and determines whether each connection interface is connected to one power consumption device. The power management circuit turns off power supply to the connection interface that is not connected to the power consumption devices. According to the current total load and the target load, the power management circuit determines an enabled number of the PSUs, thereby turning on or turning off each PSU accordingly.
    Type: Application
    Filed: January 21, 2021
    Publication date: September 30, 2021
    Inventors: Wei-Cheng Wang, Chia-Neng Yang, Chia-Cheng Chang
  • Publication number: 20210240907
    Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.
    Type: Application
    Filed: April 21, 2021
    Publication date: August 5, 2021
    Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien-Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
  • Publication number: 20210225704
    Abstract: In a method of manufacturing a semiconductor device, initial connection patterns are prepared, initial cutting patterns for cutting the initial connection patterns are prepared, non-functional connection patterns at least from the initial connection patterns are identified, final cutting patterns are prepared from the initial cutting patterns and the non-functional connection patterns, a photo mask is prepared from the final cutting patterns, a photo resist pattern is formed over a target layer by a lithography operation using the photo mask, the target layer is patterned to form openings in the target layer by using the photo resist pattern, and connection layers are formed by filling the openings with a conductive material.
    Type: Application
    Filed: December 28, 2020
    Publication date: July 22, 2021
    Inventors: Yuan-Yen LO, Chia-Cheng CHANG, Ming-Jhih KUO, Chien-Yuan CHEN