Patents by Inventor Chia-Cheng Chang

Chia-Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200391033
    Abstract: The invention relates to an electrochemical dephosphorylation technique for treating Alzheimer's disease and a use thereof. It comprises a gold electrode provided with a negative potential of ?0.2 V to ?0.6 V on a surface thereof.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Inventors: JUNG-CHIH CHEN, I-CHIU LI, KUN-CHE LI, CHING-CHENG CHUANG, MEI-LAN KO, HSIN-YU CHEN, CHIA-HSUAN CHANG, HSIN-YI TSAI, CHIEN-CHIH HSU
  • Publication number: 20200388706
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang CHEN, Chih-Ming LAI, Ching-Wei TSAI, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kuo-Cheng CHIANG, Ru-Gun LIU, Wei-Hao WU, Yi-Hsiung LIN, Chia-Hao CHANG, Lei-Chun CHOU
  • Publication number: 20200381425
    Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Inventors: Chia-Ming CHANG, Jung-Tao CHUNG, Yan-Cheng LIN, Lung-Yi TSENG
  • Patent number: 10852795
    Abstract: A method for system power management includes steps of detecting power output of plural power-supplying units (PSUs) and power consumption of plural computing node, so as to indirectly obtain real-time auxiliary power consumption of an auxiliary unit and continuously update maximum auxiliary power consumption; when one of the PSUs is malfunctioned, renewing the maximum sum of the power output of the other PSUs, and applying the difference of the renewed maximum sum of the power outputs and the maximum auxiliary power consumption as a first sum of the node power consumptions of the computing nodes; finally, according to the first sum of the node power consumptions, cutting down the power consumption of at least one of the computing nodes to a first node power consumption.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: December 1, 2020
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Wei-Cheng Wang, Chia-Cheng Chang
  • Publication number: 20200365526
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto, wherein the substrate includes a wiring structure, and a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The package further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are separated by a molding material. A first hole and a second hole are formed on the second surface of the substrate. Finally, a frame is disposed over the first surface of the substrate, wherein the frame surrounds the first semiconductor die and the second semiconductor die.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Tzu-Hung LIN, Chia-Cheng CHANG, I-Hsuan PENG, Nai-Wei LIU
  • Patent number: 10840134
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-yi Ruan
  • Patent number: 10825229
    Abstract: A projection-based frame is generated according to an omnidirectional video frame and a triangle-based projection layout. The projection-based frame has a 360-degree image content represented by triangular projection faces assembled in the triangle-based projection layout. A 360-degree image content of a viewing sphere is mapped onto the triangular projection faces via a triangle-based projection of the viewing sphere. One side of a first triangular projection face has contact with one side of a second triangular projection face, one side of a third triangular projection face has contact with another side of the second triangular projection face. One image content continuity boundary exists between one side of the first triangular projection face and one side of the second triangular projection face, and another image content continuity boundary exists between one side of the third triangular projection face and another side of the second triangular projection face.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 3, 2020
    Assignee: MEDIATEK INC.
    Inventors: Jian-Liang Lin, Hung-Chih Lin, Chia-Ying Li, Shen-Kai Chang, Chi-Cheng Ju, Chao-Chih Huang, Hui Ouyang
  • Publication number: 20200343357
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Application
    Filed: July 8, 2020
    Publication date: October 29, 2020
    Inventors: Po-Chi Wu, Chia-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 10818562
    Abstract: A method for testing a semiconductor structure includes forming a dielectric layer over a test region of a substrate. A cap layer is formed over the dielectric layer. The dielectric layer and the cap layer are annealed. The annealed cap layer is removed. A ferroelectricity of the annealed dielectric layer is in-line tested.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Shiang Lin, Chia-Cheng Ho, Chun-Chieh Lu, Cheng-Yi Peng, Chih-Sheng Chang
  • Patent number: 10811407
    Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: October 20, 2020
    Assignee: WIN SEMICONDUCTOR CORP.
    Inventors: Chia-Ming Chang, Jung-Tao Chung, Yan-Cheng Lin, Lung-Yi Tseng
  • Publication number: 20200321238
    Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Meng-Fang Hsu, Kong-Pin Chang, Chia Ming Liang
  • Patent number: 10795200
    Abstract: A display device includes a display panel, a light shielding unit and a back plate. The display panel includes a first substrate, a second substrate and an upper polarizer. The first substrate is disposed corresponding to the second substrate. The upper polarizer is disposed on the second substrate. The light shielding unit is connected to the upper polarizer. The first substrate is disposed on the back plate.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: October 6, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Chien-Chih Chen, Chia-Chun Yang, Chin-Cheng Kuo, Hsin-Tien Wu, Chih-Jen Chang
  • Patent number: 10797174
    Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Tai Chang, Tung Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
  • Patent number: 10787409
    Abstract: A method for producing a cyclohexanone dimer is provided. The method includes the steps of performing condensation of cyclohexanone in the presence of a solid acid catalyst to obtain the cyclohexanone dimer, wherein the solid acid catalyst includes metal oxide of tungsten and a carrier with Lewis acid sites and Brønsted acid sites. The method of the present disclosure has an advantage of mild reaction condition, fast reaction rate and high selectivity, thereby realizing the value of the industrial application.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: September 29, 2020
    Assignee: CHINA PETROCHEMICAL DEVELOPMENT CORPORATION, TAIPEI (TAIWAN)
    Inventors: Chih-Cheng Chang, Hong-Kai Yang, Chia-Tsen Tsai, Chia-Hui Shen
  • Patent number: 10784211
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a wiring structure. The semiconductor package structure also includes a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The semiconductor package structure further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The first semiconductor die and the second semiconductor die are separated by a molding material. In addition, the semiconductor package structure includes a first hole and a second hole formed on the second surface of the substrate.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 22, 2020
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Chia-Cheng Chang, I-Hsuan Peng, Nai-Wei Liu
  • Publication number: 20200293417
    Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.
    Type: Application
    Filed: May 29, 2020
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hung CHANG, Atul KATOCH, Chia-En HUANG, Ching-Wei WU, Donald G. MIKAN, JR., Hao-I YANG, Kao-Cheng LIN, Ming-Chien TSAI, Saman M.I. ADHAM, Tsung-Yung CHANG, Uppu Sharath CHANDRA
  • Publication number: 20200293089
    Abstract: A dock for a portable electronic device including a base, a controller, and a locking element configured to engage the portable electronic device. The locking element includes an electronic actuator configured to unlock the locking element. The controller includes a power supply in electronic communication with a utility power input connection and an external power source input connection. The power supply is configured to receive power from either the utility power input connection or the external power source input connection. The electronic processor is configured to receive an indication to unlock the locking element, and to provide power to the electronic actuator to unlock the locking element upon receiving the indication. The external power input is provided to the power supply from the external power source input connection based on no utility power input being present at the utility power input connection.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Inventors: Chia Yi Chang, Chia-Cheng Hung, Yu-Chia Huang
  • Publication number: 20200276618
    Abstract: This invention discloses a system and method for detecting a cover with an abnormal condition. The system includes a transport track for defining a sliding direction of at least one cover with a detection surface. The transport track has a detection area and a cover removal area, and includes a pair of bottom rails and a pair of side rails. The pair of bottom rails support the cover at an inclination angle so that the cover slides on the pair of bottom rails. The cover is located between the pair of side rails, and the sliding direction of the cover is defined by the pair of side rails. The detection area is used for detecting the detection surface of the cover, and the cover removal area has an outlet for removing a cover with an abnormal condition determined based on a detection result of the detection surface thereof.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Inventors: Chi-Huan Shih, Chia Kai Chang, Chang Cheng Chen
  • Patent number: D902981
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao
  • Patent number: D902982
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao