Patents by Inventor Chia-Cheng Chang

Chia-Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200276618
    Abstract: This invention discloses a system and method for detecting a cover with an abnormal condition. The system includes a transport track for defining a sliding direction of at least one cover with a detection surface. The transport track has a detection area and a cover removal area, and includes a pair of bottom rails and a pair of side rails. The pair of bottom rails support the cover at an inclination angle so that the cover slides on the pair of bottom rails. The cover is located between the pair of side rails, and the sliding direction of the cover is defined by the pair of side rails. The detection area is used for detecting the detection surface of the cover, and the cover removal area has an outlet for removing a cover with an abnormal condition determined based on a detection result of the detection surface thereof.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Inventors: Chi-Huan Shih, Chia Kai Chang, Chang Cheng Chen
  • Patent number: 10763365
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Ching-Wei Tsai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kuo-Cheng Ching, Ru-Gun Liu, Wei-Hao Wu, Yi-Hsiung Lin, Chia-Hao Chang, Lei-Chun Chou
  • Patent number: 10756199
    Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chen, Meng-Shu Lin, Liang-Yin Chen, Xiong-Fei Yu, Syun-Ming Jang, Hui-Cheng Chang
  • Publication number: 20200251469
    Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.
    Type: Application
    Filed: February 4, 2019
    Publication date: August 6, 2020
    Inventors: Chia-Ming CHANG, Jung-Tao CHUNG, Yan-Cheng LIN, Lung-Yi TSENG
  • Publication number: 20200251461
    Abstract: The light source device includes a substrate, a light emitting unit mounted on the substrate, a frame disposed on the substrate, a metal shield fixed to an inner side of the frame and electrically coupled to the substrate, a light permeable member disposed on the frame, a cover plate disposed on the light permeable member and fixed to the frame, a detection unit electrically coupled to the substrate, and an uplift block that provides for the substrate to be disposed thereon.
    Type: Application
    Filed: January 30, 2020
    Publication date: August 6, 2020
    Inventors: Hsin-Wei Tsai, Jui-Lin Tsai, Chia-Cheng Wu, YOU-CHEN YU, CHIEN-TIEN WANG, TAI-WEN TSAI, Pai-Hao Chang, SHU-HUA YANG, YU-HUNG SU
  • Patent number: 10734509
    Abstract: A nitride semiconductor epitaxial stack structure including: a silicon substrate; an AlN nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including a first superlattice epitaxial structure, a first GaN-based layer disposed on the first superlattice epitaxial structure, and a second superlattice epitaxial structure disposed on the first GaN based layer; a channel layer disposed on the buffer structure; and a barrier layer disposed on the channel layer; wherein the first superlattice epitaxial structure includes a first average Al composition ratio, the first GaN-based layer includes a first Al composition ratio, the_second superlattice epitaxial structure includes a second average Al composition ratio; wherein an Al composition ratio of the AlN nucleation layer?the first average Al composition ratio of the first superlattice epitaxial structure>the first Al composition ratio of the first GaN based layer>the second
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: August 4, 2020
    Assignee: Epistar Corporation
    Inventors: Shang Ju Tu, Ya Yu Yang, Chia Cheng Liu, Tsung Cheng Chang
  • Publication number: 20200241192
    Abstract: A light guide plate includes a main body, first stripe structures and second stripe structures. The main body has an optical surface, a light-incident surface and an opposite light-incident surface. The main body has a hole passing through the optical surface, and the optical surface has a first region and a second region which are separated by an imaginary line. The imaginary line intersects the hole. The hole has a first side near the opposite light-incident surface and a second side near the light-incident surface. A portion of each of the first stripe structures is disposed in the first region. The second stripe structures are disposed in the second region. An extending direction of at least one portion of each first stripe structure is vertical to the light-incident surface, and a portion of the second stripe structures extends to the first side of the hole near the opposite light-incident surface.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: Chia-Yin CHANG, Po-Chang HUANG, Kun-Cheng LIN
  • Publication number: 20200243524
    Abstract: A semiconductor device includes first and second nanowire structures, first and second annular hafnium oxide layers, first and second annular cap layers, and first and second metal gate electrodes. The first and second nanowire structures are suspended over a substrate and respectively have an n-channel region and a p-channel region. The first and second annular hafnium oxide layers encircle the n-channel region and the p-channel region, respectively. The first and second annular cap layers encircle the first and second annular hafnium oxide layers, respectively. The first and second annular cap layers are made of a same material that is lanthanum oxide, yttrium oxide, or strontium oxide. The first and second metal gate electrodes encircle the first and second annular cap layers, respectively. The first and second metal gate electrodes have a same metal composition.
    Type: Application
    Filed: April 9, 2020
    Publication date: July 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yuan CHANG, Xiong-Fei YU, Hui-Cheng CHANG
  • Publication number: 20200233255
    Abstract: A display device includes a liquid crystal display (LCD) panel, a diffusion film, and an adhesive frame. The adhesive frame is arranged between the LCD panel and the diffusion film. The diffusion film is configured to diffuse incident light incident on the diffusion film. The adhesive frame includes a first surface and an opposite second surface. The first surface of the adhesive frame is coupled to a periphery of the LCD panel. The second surface of the adhesive frame is coupled to a periphery of the diffusion film.
    Type: Application
    Filed: February 14, 2019
    Publication date: July 23, 2020
    Inventors: HUI-CHENG LIN, CHIA-HUANG CHANG
  • Patent number: 10705934
    Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Donald G. Mikan, Jr., Hao-I Yang, Kao-Cheng Lin, Ming-Chien Tsai, Saman M. I. Adham, Tsung-Yung Chang, Uppu Sharath Chandra
  • Patent number: 10707835
    Abstract: A wireless receiving device is provided. The wireless receiving device includes a first passive mixer and a common gate amplifier. The first passive mixer receives an oscillation signal. The common gate amplifier is coupled to the first passive mixer, and automatically adjusts the input impedance of the common gate amplifier according to the oscillation frequency of the oscillation signal.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: July 7, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Jen Liang, Yen-Cheng Kuan, Ching-Wen Chiang, Mau-Chung Chang
  • Patent number: 10707282
    Abstract: A display may have organic light-emitting diode pixels formed from thin-film circuitry. An organic layer including planarization layers and a pixel definition layer may overlap the thin-film circuitry. Thin-film encapsulation may overlap the organic layer. The thin-film encapsulation may be formed from an organic dielectric layer interposed between two layers of inorganic dielectric material. A strip of peripheral crack-stopper structures may run along an edge of the display and may surround the array of pixels. The crack-stopper structures may include parallel inorganic lines formed from a first inorganic layer such as an inorganic layer of the thin-film circuitry. A strip of the organic layer may overlap the parallel inorganic lines. The crack-stopper structures may have parallel tapered polymer lines. The polymer lines may be overlapped by a second inorganic dielectric layer formed from the inorganic material of the thin-film encapsulation layer.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 7, 2020
    Assignee: Apple Inc.
    Inventors: Chih Jen Yang, Prashant Mandlik, Chia-Hao Chang, Chien-Chung Wang, Te-Hua Teng, Yu Cheng Chen
  • Publication number: 20200211258
    Abstract: A projection-based frame is generated according to an omnidirectional video frame and a triangle-based projection layout. The projection-based frame has a 360-degree image content represented by triangular projection faces assembled in the triangle-based projection layout. A 360-degree image content of a viewing sphere is mapped onto the triangular projection faces via a triangle-based projection of the viewing sphere. One side of a first triangular projection face has contact with one side of a second triangular projection face, one side of a third triangular projection face has contact with another side of the second triangular projection face. One image content continuity boundary exists between one side of the first triangular projection face and one side of the second triangular projection face, and another image content continuity boundary exists between one side of the third triangular projection face and another side of the second triangular projection face.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 2, 2020
    Inventors: Jian-Liang Lin, Hung-Chih Lin, Chia-Ying Li, Shen-Kai Chang, Chi-Cheng Ju, Chao-Chih Huang, Hui Ouyang
  • Publication number: 20200203499
    Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a ferroelectric composite material layer, a gate, a source and a drain. The channel layer and the barrier layer having a recess are disposed on the substrate in sequence. The ferroelectric composite material layer including a first dielectric layer, a charge trapping layer, a first ferroelectric material layer, a second dielectric layer and a second ferroelectric material layer is disposed in the recess. The gate is disposed on the ferroelectric composite material layer. The source and the drain are disposed on the barrier layer.
    Type: Application
    Filed: March 4, 2020
    Publication date: June 25, 2020
    Inventors: Edward Yi CHANG, Shih-Chien LIU, Chung-Kai HUANG, Chia-Hsun WU, Ping-Cheng HAN, Yueh-Chin LIN, Ting-En HSIEH
  • Patent number: 10692750
    Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Meng-Fang Hsu, Kong-Pin Chang, Chia Ming Liang
  • Publication number: 20200195231
    Abstract: A wireless receiving device is provided. The wireless receiving device includes a first passive mixer and a common gate amplifier. The first passive mixer receives an oscillation signal. The common gate amplifier is coupled to the first passive mixer, and automatically adjusts the input impedance of the common gate amplifier according to the oscillation frequency of the oscillation signal.
    Type: Application
    Filed: December 26, 2018
    Publication date: June 18, 2020
    Inventors: Chia-Jen LIANG, Yen-Cheng KUAN, Ching-Wen CHIANG, Mau-Chung CHANG
  • Publication number: 20200184286
    Abstract: A smart medication identifying system is disclosed herein. It comprises a processing device including a first processing module, a scanning module electrically connected to the first processing module and a first reminding module electrically connected to the first processing module; a cloud storage device electrically connected to the processing device and having a storage module, a login module electrically connected to the storage module, and a medication information database electrically connected to the storage module; and a medication identifying device electrically connected to the processing device and the cloud storage device and having a second processing module, an image identifying module electrically connected to the second processing module and a second reminding module electrically connected to the second processing module.
    Type: Application
    Filed: June 28, 2019
    Publication date: June 11, 2020
    Inventors: WAN-JUNG CHANG, LIANG-BI CHEN, CHIA-HAO HSU, YI-DE YAN, ZHI-CHENG QIU, TZU-CHIN YANG, CHAO-YAN LIN, CHENG-PEI LIN
  • Publication number: 20200185440
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 11, 2020
    Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
  • Publication number: 20200167113
    Abstract: A display apparatus having a signal connection to a host is provided. The display apparatus includes a display module and a display controller. The display controller is configured to receive an on-screen-display (OSD) control signal and an image signal from the host, wherein the OSD control signal is generated in response to a specific event detected by the host. The host overwrites a specific region of the image signal with an OSD interface corresponding to the OSD control signal to generate an output image, and the display controller displays the output image on the display module.
    Type: Application
    Filed: September 5, 2019
    Publication date: May 28, 2020
    Applicant: GIGA-BYTE TECHNOLOGY CO.,LTD.
    Inventors: Wu-Chuan CHEN, Shih-Pin CHANG, Yu-Cheng LIOU, Chia-En LIU
  • Patent number: D891504
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 28, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao