Patents by Inventor Chia-Cheng Chang

Chia-Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190391626
    Abstract: A control method is applied to a redundant power supply device, with the redundant power supply device is connected to a power demanding device and comprises a plurality of power supply units, with said control method comprising: detecting and calculating a required electrical power value of the power demanding device, and determining an operation quantity of the power supply units according to the required electrical power value and a plurality of efficient operation data for generating a control command, and selectively controlling the redundant power supply device according to the control command. Additionally, wherein the plurality of efficient operation data indicates a relationship between supplied power of the redundant power supply device and the operation quantity of the power supply units, and the relationship is associated with a power supply efficiency of the redundant power supply device.
    Type: Application
    Filed: December 21, 2018
    Publication date: December 26, 2019
    Applicant: GIGA-BYTE TECHNOLOGY CO.,LTD.
    Inventors: Wei-Cheng WANG, Chia-Cheng CHANG
  • Publication number: 20190393325
    Abstract: Embodiments disclosed herein relate generally to forming a structure, e.g., in high aspect ratio trenches. In an embodiment, a method for semiconductor processing is provided. The method includes forming fins on a substrate. Sidewalls of the fins and a bottom surface between the sidewalls of the fins define a trench therebetween. The method includes forming a gate structure over the fins. The gate structure has a sidewall with a defect region formed therein. The method includes forming a filling layer to fill the defect region in the sidewall of the gate structure.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Chia-Ao Chang, Chien-Hao Chen, De-Wei Yu, Yung-Cheng Lu
  • Publication number: 20190386061
    Abstract: In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure comprised of conductive or magnetic material at least partially surrounds the chip. The magnetic-field-shielding structure comprises a sidewall region that laterally surrounds the chip, an upper region extending upward from the sidewall region, and a lower region extending downward from the sidewall region. At least one of the upper region and/or lower region terminate at an opening over the chip.
    Type: Application
    Filed: April 10, 2019
    Publication date: December 19, 2019
    Inventors: Kuo-An Liu, Chung-Cheng Wu, Harry-Hak-Lay Chuang, Gwan-Sin Chang, Tien-Wei Chiang, Zhiqiang Wu, Chia-Hsiang Chen
  • Patent number: 10505040
    Abstract: A method for manufacturing a semiconductor device comprises forming a first fin and a second fin on a first active region and a second active region of a semiconductor substrate, respectively. A first dummy gate is formed over the first fin and a second dummy gate is formed over the second fin, wherein the first dummy gate has a first gate width along a lengthwise direction of the first fin, the second dummy gate has a second gate width along the lengthwise direction of the second fin, the first gate width is different from the second gate width. At least one of the first dummy gate and the second dummy gate is removed. A ferroelectric layer is then formed over the semiconductor substrate, in which the first dummy gate and/or the second dummy gate is removed. At least one metal gate electrode is formed on the ferroelectric layer.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Cheng Ho, Ming-Shiang Lin, Cheng-Yi Peng, Chun-Chieh Lu, Chih-Sheng Chang, Carlos H. Diaz
  • Patent number: 10497792
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Patent number: 10497689
    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor die and a first memory die disposed on a first surface of a substrate, wherein the first memory die comprises a first edge facing the semiconductor die. The semiconductor die includes a peripheral region having a second edge facing the first edge of the first memory die and a third edge opposite to the second edge. The semiconductor die also includes a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 3, 2019
    Assignee: MEDIATEK INC.
    Inventors: Chia-Cheng Chang, I-Hsuan Peng, Tzu-Hung Lin
  • Publication number: 20190341479
    Abstract: A nitride semiconductor epitaxial stack structure including: a silicon substrate; an AlN nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including a first superlattice epitaxial structure, a first GaN-based layer disposed on the first superlattice epitaxial structure, and a second superlattice epitaxial structure disposed on the first GaN based layer; a channel layer disposed on the buffer structure; and a barrier layer disposed on the channel layer; wherein the first superlattice epitaxial structure includes a first average Al composition ratio, the first GaN-based layer includes a first Al composition ratio, the_second superlattice epitaxial structure includes a second average Al composition ratio; wherein an Al composition ratio of the AlN nucleation layer?the first average Al composition ratio of the first superlattice epitaxial structure>the first Al composition ratio of the first GaN based layer>the second
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: SHANG JU TU, YA YU YANG, CHIA CHENG LIU, TSUNG CHENG CHANG
  • Publication number: 20190330376
    Abstract: A recombinant protein drug includes a parent protein drug coupled with a modified kininogen-1 peptide. The modified kininogen-1 peptide has the sequence of SEQ ID NO:2 or a homolog having a sequence identity of 80% or higher. The parent protein drug is a bispecific antibody having a first targeting domain linked by a bridging domain with a second targeting domain. The modified kininogen-1 peptide is fused between the first targeting domain and the bridging domain, or between the bridging domain and the second targeting domain. A method for increasing the serum half-life of a protein drug includes constructing a fusion protein comprising the protein drug coupled with a modified kininogen-1 peptide.
    Type: Application
    Filed: December 29, 2017
    Publication date: October 31, 2019
    Applicant: Development Center for Biotechnology
    Inventors: Chen-Li Chien, Gregory Jiann Chen, Chuan-Lung Hsu, Jei-Hwa Yu, Hsien-Yu Tsai, Show-Shan Sheu, Wei-Jung Chang, Chia-Cheng Wu
  • Patent number: 10462484
    Abstract: A video encoding method includes: setting a 360-degree Virtual Reality (360 VR) projection layout of projection faces, wherein the projection faces have a plurality of triangular projection faces located at a plurality of positions in the 360 VR projection layout, respectively; encoding a frame having a 360-degree image content represented by the projection faces arranged in the 360 VR projection layout to generate a bitstream; and for each position included in at least a portion of the positions, signaling at least one syntax element via the bitstream, wherein the at least one syntax element is set to indicate at least one of an index of a triangular projection view filled into a corresponding triangular projection face located at the position and a rotation angle of content rotation applied to the triangular projection view filled into the corresponding triangular projection face located at the position.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: October 29, 2019
    Assignee: MEDIATEK INC.
    Inventors: Jian-Liang Lin, Hung-Chih Lin, Chia-Ying Li, Shen-Kai Chang, Chi-Cheng Ju
  • Patent number: 10462928
    Abstract: A composite cable assembly includes flat cables, a cable unit and fastening units. Each flat cable includes conductor assemblies and a shielding layer covering the conductor assemblies. The cable unit includes transmission lines. The transmission lines are arranged horizontally and in contact with the shielding layer of the flat cable closest to the transmission lines. The cable unit contacts the flat cable closest to the cable unit, the cable unit and each flat cable are together bent to form bent portions and extension sections connected to the bent portions. Each two fastening units are arranged spaced apart at two sides of a corresponding bent portion. Each extension section has the same length when the cable unit and each flat cable are moved in a movement direction to extend or collapse.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: October 29, 2019
    Assignee: SUPER MICRO COMPUTER INC.
    Inventors: Hsiao-Chung Chen, Tan-Hsin Chang, Chia-Cheng Lu, Chih-Wei Chen
  • Patent number: 10431535
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming an antenna structure in contact with one side of a circuit structure of a packaging substrate, and disposing an electronic component on the other side of the circuit structure. As such, the antenna structure is integrated with the packaging substrate, thereby reducing the thickness of the electronic package and improving the efficiency of the antenna structure.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: October 1, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Jui-Feng Chen, Chia-Cheng Hsu, Wen-Jung Tsai, Chia-Cheng Chen, Cheng Kai Chang
  • Patent number: 10410969
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package overlying a portion of the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure, a first semiconductor die and a molding compound. The first semiconductor die is disposed on a first surface of the first RDL structure and electrically coupled to the first RDL structure. The molding compound is positioned overlying the first semiconductor die and the first surface of the first RDL structure. The second semiconductor package includes a first memory die and a second memory die vertically stacked on the first memory die. The second memory die is electrically coupled to first memory die by through silicon via (TSV) interconnects formed passing through the second memory die.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: September 10, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Chia-Cheng Chang, I-Hsuan Peng
  • Publication number: 20190252459
    Abstract: A light-emitting device includes a first semiconductor layer having an uppermost surface and a bottommost surface; a first light-emitting structure and a second light-emitting structure formed on the same first semiconductor layer, wherein the first semiconductor layer is continuous; a first trench formed between the first and the second light-emitting structures; and a second electrode formed on the second semiconductor layer and including a second pad and a plurality of second extending parts extending from the second pad; wherein the second pad is between the first and the second light-emitting structures, and the plurality of second extending parts extends to the first and the second light-emitting structures, respectively; wherein the first trench passes through the uppermost surface but does not extend to the bottommost surface; wherein the first trench includes an equal width in a top view.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Chen OU, Chun-Wei CHANG, Chih-Wei WU, Sheng-Chih WANG, Hsin-Mei TSAI, Chia-Chen TSAI, Chuan-Cheng CHANG
  • Publication number: 20190252246
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-Yi Ruan
  • Publication number: 20190245057
    Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Chia-Cheng Chen, Meng-Shu Lin, Liang-Yin Chen, Xiong-Fei Yu, Syun-Ming Jang, Hui-Cheng Chang
  • Publication number: 20190227256
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a carrier, a base, and a first driving assembly. The carrier holds an optical element with an optical axis. The carrier is movably connected to the base. The first driving assembly drives the carrier to move relative to the base. The first driving assembly includes a driving coil disposed on the carrier, and the direction of the winding axis of the driving coil is different from the direction of the optical axis. The carrier has an abutting surface, which faces and is in direct contact with the driving coil. The maximum size of the abutting surface is greater than the maximum size of the driving coil in the direction of the optical axis.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 25, 2019
    Inventors: Chen-Chi KUO, Chia-Hsiu LIU, Yen-Cheng CHEN, Shao-Chung CHANG, Sin-Jhong SONG
  • Publication number: 20190227337
    Abstract: An optical driving mechanism is provided, including a movable portion, a bottom plate and a biasing assembly. The movable portion is configured to sustain an optical element having an optical axis. The bottom plate has a moving member. The biasing assembly has at least one biasing element for driving the movable portion to move relative to the bottom plate. The bottom plate defines a first electrical connection portion and a second electrical connection portion, and the biasing element is connected to the first and second electrical connection portions. The first electrical connection portion has a fixed body, an insulating layer and a conductive layer, which are sequentially overlapped along the optical axis. The conductive layer is directly and electrically connected to the biasing element. When viewed along the optical axis, the insulating layer protrudes from the fixed body and the conductive layer.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 25, 2019
    Inventors: Chen-Chi KUO, Chia-Hsiu LIU, Yen-Cheng CHEN, Shao-Chung CHANG, Sin-Jhong SONG
  • Patent number: 10361295
    Abstract: A nitride semiconductor epitaxial stack structure including: a Silicon substrate; an aluminum-including nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including: a first superlattice epitaxial structure, a first GaN based thick layer disposed on the first superlattice epitaxial structure, a second superlattice epitaxial structure disposed on the first GaN based thick layer, and a second GaN based thick layer disposed on the second superlattice epitaxial structure; a channel layer disposed on the buffer structure; a barrier layer disposed on the channel layer; and a two dimensional electron gas layer disposed near an interface between the channel layer and the barrier layer, wherein the total thickness of the first GaN based thick layer and the second GaN based thick layer is more than 2 micrometers.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: July 23, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Shang Ju Tu, Ya Yu Yang, Chia Cheng Liu, Tsung Cheng Chang
  • Patent number: 10332978
    Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Yu-Cheng Tung, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Publication number: 20190179386
    Abstract: A method for system power management includes steps of detecting power output of plural power-supplying units (PSUs) and power consumption of plural computing node, so as to indirectly obtain real-time auxiliary power consumption of an auxiliary unit and continuously update maximum auxiliary power consumption; when one of the PSUs is malfunctioned, renewing the maximum sum of the power output of the other PSUs, and applying the difference of the renewed maximum sum of the power outputs and the maximum auxiliary power consumption as a first sum of the node power consumptions of the computing nodes; finally, according to the first sum of the node power consumptions, cutting down the power consumption of at least one of the computing nodes to a first node power consumption.
    Type: Application
    Filed: July 26, 2018
    Publication date: June 13, 2019
    Inventors: Wei-Cheng Wang, Chia-Cheng Chang