Abstract: Semiconductor devices having capacitor arrays and methods of forming the same. A semiconductor device is formed including a capacitor array. The capacitor array includes a plurality of operational capacitors formed along a diagonal of the capacitor array. The capacitor array also includes a plurality of dummy capacitors formed substantially symmetrically about the plurality of operational capacitors in the capacitor array. A first operational capacitor is formed at a first edge of the capacitor array. Each one of the plurality of operational capacitors is electrically coupled to a non-adjacent other one of the plurality of operational capacitors.

Abstract: Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.

Abstract: One or more techniques or systems for forming an integrated circuit (IC) or associated IC structure are provided herein. In some embodiments, the IC includes a junction gate field effect transistor (JFET) and a lateral vertical bipolar junction transistor (LVBJT). For example, the JFET and the LVBJT are formed in a same region, such as a substrate. In some embodiments, the JFET and the LVBJT are at least one of adjacent or share one or more features. In this manner, a reliable IC is provided, thus enabling power amplification, for example.

Abstract: A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.

Abstract: In at least one embodiment, a method of manufacturing a varactor includes forming a well over a substrate. The well has a first type doping. A first source region and a second source region are formed in the well, and the first source region and the second source region have a second type doping. A drain region is formed in the well, and the drain region has the first type doping. A first gate region is formed over the well between the drain region and the first source region. Moreover, a second gate region is formed over the well between the drain region and the second source region.

Abstract: A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.

Abstract: A device includes a first MOM capacitor; a second MOM capacitor directly over and vertically overlapping the first MOM capacitor, wherein each of the first and the second MOM capacitors includes a plurality of parallel capacitor fingers; a first and a second port electrically coupled to the first MOM capacitor; and a third and a fourth port electrically coupled to the second MOM capacitor. The first, the second, the third, and the fourth ports are disposed at a surface of a respective wafer.

Abstract: Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.

Abstract: Semiconductor devices having capacitor arrays and methods of forming the same. A semiconductor device is formed including a capacitor array. The capacitor array includes a plurality of operational capacitors formed along a diagonal of the capacitor array. The capacitor array also includes a plurality of dummy capacitors formed substantially symmetrically about the plurality of operational capacitors in the capacitor array. A first operational capacitor is formed at a first edge of the capacitor array. Each one of the plurality of operational capacitors is electrically coupled to a non-adjacent other one of the plurality of operational capacitors.

Abstract: An isolation structure in a semiconductor device absorbs electronic noise and prevents substrate leakage currents from reaching other devices and signals. The isolation structure provides a duality of deep N-well (“DNW”) isolation structures surrounding an RF device or other source of electronic noise. The DNW isolation structures extend into the substrate at a depth of at least about 2.5 ?m and may be coupled to VDD. P+ guard rings are also provided in some embodiments and are provided inside, outside or between the dual DNW isolation structures.

Abstract: Apparatus and methods for a MOS varactor structure are disclosed An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.

Abstract: An integrated circuit device is disclosed. An exemplary integrated circuit device includes: a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed over the base portion of the fin structure. The collector portion is a first doped region including a first type dopant, and is coupled with a first terminal for electrically biasing the collector portion. The emitter portion is a second doped region including the first type dopant, and is coupled with a second terminal for electrically biasing the emitter portion. The base portion is a third doped region including a second type dopant opposite the first type, and is coupled with a third terminal for electrically biasing the base portion. The gate structure is coupled with a fourth terminal for electrically biasing the gate structure, such that the gate structure controls a path of current through the base portion.

Abstract: A device includes a well region over a substrate, and a heavily doped well region over the well region, wherein the well region and the heavily doped well region are of a same conductivity type. A gate dielectric is formed on a top surface of the heavily doped well region. A gate electrode is formed over the gate dielectric. A source region and a drain region are formed on opposite sides of the heavily doped well region. The source region and the drain region have bottom surfaces contacting the well region, and wherein the source region and the drain region are of opposite conductivity types.

Abstract: In at least one embodiment, a method of manufacturing a varactor includes forming a well over a substrate. The well has a first type doping. A first source region and a second source region are formed in the well, and the first source region and the second source region have a second type doping. A drain region is formed in the well, and the drain region has the first type doping. A first gate region is formed over the well between the drain region and the first source region. Moreover, a second gate region is formed over the well between the drain region and the second source region.

Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.

Abstract: Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed.

Abstract: Apparatus and methods for a MOS varactor structure are disclosed An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.

Abstract: A device includes a first MOM capacitor; a second MOM capacitor directly over and vertically overlapping the first MOM capacitor, wherein each of the first and the second MOM capacitors includes a plurality of parallel capacitor fingers; a first and a second port electrically coupled to the first MOM capacitor; and a third and a fourth port electrically coupled to the second MOM capacitor. The first, the second, the third, and the fourth ports are disposed at a surface of a respective wafer.

Abstract: A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate.

Abstract: An integrated circuit device is disclosed. An exemplary integrated circuit device includes: a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed over the base portion of the fin structure. The collector portion is a first doped region including a first type dopant, and is coupled with a first terminal for electrically biasing the collector portion. The emitter portion is a second doped region including the first type dopant, and is coupled with a second terminal for electrically biasing the emitter portion. The base portion is a third doped region including a second type dopant opposite the first type, and is coupled with a third terminal for electrically biasing the base portion. The gate structure is coupled with a fourth terminal for electrically biasing the gate structure, such that the gate structure controls a path of current through the base portion.