Patents by Inventor Chia-Chung Chen

Chia-Chung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HVMOS Reliability Evaluation using Bulk Resistances as Indices
    Publication number: 20180277539
    Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
    Type: Application
    Filed: June 1, 2018
    Publication date: September 27, 2018
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Tse-Hua Lu
  • MOS Devices with Mask Layers and Methods for Forming the Same
    Publication number: 20180226488
    Abstract: A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Inventors: Chu-Fu Chen, Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang
  • JUNCTION GATE FIELD-EFFECT TRANSISTOR (JFET) HAVING SOURCE/DRAIN AND GATE ISOLATION REGIONS
    Publication number: 20180166547
    Abstract: A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region contacts one of the source and drain regions at an interface, and the at least one gate region is isolated from the other of the source and drain regions. A dielectric layer covers the interface while exposing portions of the gate region and the one of the source and drain regions.
    Type: Application
    Filed: January 29, 2018
    Publication date: June 14, 2018
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang
  • HVMOS reliability evaluation using bulk resistances as indices
    Patent number: 9991260
    Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Tse-Hua Lu
  • MOS devices with mask layers and methods for forming the same
    Patent number: 9947762
    Abstract: A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chu-Fu Chen, Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang
  • Junction gate field-effect transistor (JFET) having source/drain and gate isolation regions
    Patent number: 9882012
    Abstract: A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region contacts one of the source and drain regions at an interface, and the at least one gate region is isolated from the other of the source and drain regions. A dielectric layer covers the interface while exposing portions of the gate region and the one of the source and drain regions.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang
  • SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20180006146
    Abstract: A semiconductor device includes a plurality of fins over a substrate. Each fin of the plurality of fins extends in a first direction substantially perpendicular to a bottom surface of the substrate, and each fin of the plurality of fins comprises a first doped region having a first dopant type. The semiconductor device further includes an isolation region over the substrate between a first fin of the plurality of fins and a second fin of the plurality of fins adjacent to the first fin. The semiconductor device further includes a second doped region extends continuously across the isolation region, the second doped region extends into each fin of the plurality of fins, and a dimension of the second doped region in the isolation region in a second direction perpendicular to the first direction is less than a dimension of the at least one isolation region in the second direction.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 4, 2018
    Inventors: Chewn-Pu JOU, Tzu-Jin YEH, Chia-Chung CHEN
  • BURIED CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20170352660
    Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 7, 2017
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Fu-Huan Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Han-Min Tsai, Hong-Lin Chu
  • HIGH SPEED SEMICONDUCTOR DEVICE
    Publication number: 20170345821
    Abstract: A semiconductor device includes a fin extending from a substrate, a first source/drain feature, a second source/drain feature, and a gate structure on the fin. A distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature.
    Type: Application
    Filed: September 2, 2016
    Publication date: November 30, 2017
    Inventors: Shu Fang FU, Chi-Feng HUANG, Chia-Chung CHEN, Victor Chiang LIANG, Fu-Huan TSAI
  • High voltage metal-oxide-metal (HV-MOM) device, HV-MOM layout and method of making the HV-MOM device
    Patent number: 9825118
    Abstract: A high voltage metal-oxide-metal (HV-MOM) layout includes a first conductive element. The first element includes a first leg extending in a first direction, a second leg connected to the first leg, the second leg extending in a second direction different from the first direction, and a third leg connected to the second leg, the third leg extending in a first direction. The HV-MOM layout further includes a second conductive element separated from the first conductive element by a space. The second conductive element includes a serpentine structure, wherein the serpentine structure is enclosed on at least three sides by the first conductive element. The HV-MOM layout further includes a dielectric material filling the space between the first conductive element and the second conductive element.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chung Chen, Shu Fang Fu, Chang-Sheng Liao
  • Semiconductor device and semiconductor system
    Patent number: 9824985
    Abstract: A semiconductor device is provided. The semiconductor device includes a seal ring and a noise-absorbing circuit. The noise-absorbing circuit is electrically connected between the seal ring and a ground pad. The noise-absorbing circuit includes at least one capacitor and at least one inductor to form a first noise-absorbing path, a second noise-absorbing path and a third noise-absorbing path.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shuo-Chun Chou, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang
  • FinFET Varactor with Low Threshold Voltage and Method of Making the Same
    Publication number: 20170317073
    Abstract: Disclosed is a FinFET varactor with low threshold voltage and methods of making the same. A disclosed method includes receiving a semiconductor layer over a substrate and having channel, source, and drain regions. The method includes forming a well in the semiconductor layer to have a first dopant, and implanting a second dopant into the well. The first and second dopants are of opposite doping types. A first portion of the well has a higher concentration of the second dopant than the first dopant. A second portion of the well under the first portion has a higher concentration of the first dopant than the second dopant. The method further includes forming a gate stack over the channel region, and forming source and drain features in the source and drain regions. The first portion of the well electrically connects the source and drain features.
    Type: Application
    Filed: December 29, 2016
    Publication date: November 2, 2017
    Inventors: Fu-Huan Tsai, Han-Min Tsai, Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang
  • FinFET having isolation structure and method of forming the same
    Patent number: 9799753
    Abstract: A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, an isolation structure over the upper surface of the substrate and surrounding a lower portion of the fin structure, and a first doped region at least partially embedded in an upper portion of the fin structure. The fin structure extends along a first direction. The first doped region has a first type doping different from that of the fin structure.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang
  • Bipolar junction transistor layout
    Patent number: 9780089
    Abstract: A bipolar junction transistor includes an emitter, a base contact, a collector and a shallow trench isolation. The base contact has two base fingers that form a corner to receive the emitter. The collector has two collector fingers extending along the base fingers of the base contact. The shallow trench isolation is disposed in between the emitter and the base contact and in between the base contact and the collector.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Min Tsai, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Hsiao-Chun Lee, Shou-Chun Chou, Shu-Fang Fu
  • Power cell and power cell circuit for a power amplifier
    Patent number: 9780211
    Abstract: A power cell includes a fin over a substrate, the fin extending in a direction substantially perpendicular to a bottom surface of the substrate. The fin includes a first dopant type. The power cell further includes at least one isolation region over the substrate between the fin and an adjacent fin. The power cell further includes a gate structure in contact with the fin and the at least one isolation region, wherein the gate structure comprises a doped region in the fin, wherein the doped region has a second dopant type different from the first dopant type and the doped region defines a channel region in the fin.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chewn-Pu Jou, Tzu-Jin Yeh, Chia-Chung Chen
  • Circuits and methods of testing a device under test using the same
    Patent number: 9772366
    Abstract: A method of testing a device under test (DUT) connected between first and second DUT nodes includes generating a set of control signals, and in response to the set of control signals, disconnecting a first voltage node from a first DUT node, connecting a second voltage node to the first DUT node, periodically connecting and disconnecting a third voltage node to and from the second DUT node at a predetermined frequency, disconnecting a fourth voltage node from the second DUT node when the third voltage node is connected to the second DUT node, and connecting the fourth voltage node to the second DUT node when the third voltage node is disconnected from the second DUT node. A circuit that performs the method is also disclosed.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shuo-Chun Chou, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang
  • Buried channel semiconductor device and method for manufacturing the same
    Patent number: 9761584
    Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Fu-Huan Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Han-Min Tsai, Hong-Lin Chu
  • FinFET Having Isolation Structure and Method of Forming the Same
    Publication number: 20170250267
    Abstract: A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, a first isolation structure over the upper surface of the substrate, and a second isolation structure. The fin structure extends along a first direction and comprising a lower portion and an upper portion. The first isolation structure surrounds the lower portion of the fin structure. The second isolation structure is at least partially embedded in the upper portion of the fin structure.
    Type: Application
    Filed: May 15, 2017
    Publication date: August 31, 2017
    Inventors: Chia-Chung Chen, Fu-Huan Tsai, Feng Yuan
  • RF Switch on High Resistive Substrate
    Publication number: 20170229406
    Abstract: A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Shu Fang Fu, Tzu-Jin Yeh, Chewn-Pu Jou
  • FinFET having isolation structure and method of forming the same
    Patent number: 9653542
    Abstract: A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, a first isolation structure over the upper surface of the substrate, and a second isolation structure. The fin structure extends along a first direction and comprising a lower portion and an upper portion. The first isolation structure surrounds the lower portion of the fin structure. The second isolation structure is at least partially embedded in the upper portion of the fin structure.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Fu-Huan Tsai, Feng Yuan