Patents by Inventor Chia-Chung Chen

Chia-Chung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RF Switch on High Resistive Substrate
    Publication number: 20190259715
    Abstract: A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Shu Fang Fu, Tzu-Jin Yeh, Chewn-Pu Jou
  • Integrated Circuit Devices with Well Regions
    Publication number: 20190252258
    Abstract: A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Mingo Liu
  • TRANSISTOR HAVING ASYMMETRIC THRESHOLD VOLTAGE, BUCK CONVERTER AND METHOD OF FORMING SEMICONDUCTOR DEVICE
    Publication number: 20190165678
    Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region under the gate structure. The transistor further includes a source in the substrate adjacent a first side of the gate structure. The transistor further includes a drain in the substrate adjacent a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The transistor further includes a first lightly doped drain (LDD) region adjacent the source. The transistor further includes a second LDD region adjacent the drain. The transistor further includes a doping extension region adjacent the first LDD region.
    Type: Application
    Filed: March 28, 2018
    Publication date: May 30, 2019
    Inventors: Chu Fu CHEN, Chi-Feng HUANG, Chia-Chung CHEN, Chin-Lung CHEN, Victor Chiang LIANG, Chia-Cheng PAO
  • High-speed semiconductor device and method for forming the same
    Patent number: 10304945
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate structure over a fin structure. The method includes forming a hard mask layer over the gate structure. The hard mask layer has a first opening spaced apart from a first side of the gate structure by a first distance and a second opening spaced apart from a second side of the gate structure by a second distance that is different from the first distance. The method also includes removing the fin structure not covered by the hard mask layer. The method further includes forming a first source/drain feature in the fin structure and filling the first opening of the hard mask layer. The method further includes forming a second source/drain feature in the fin structure and filling the second opening of the hard mask layer.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Victor Chiang Liang, Chia-Chung Chen, Chi-Feng Huang, Shu-Fang Fu
  • SEMICONDUCTOR DEVICE
    Publication number: 20190157408
    Abstract: A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer, a metal layer, and a semiconductor layer. The metal layer is disposed on the gate dielectric layer. The semiconductor layer is disposed on the gate dielectric layer. The metal layer surrounds the semiconductor layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Meng-Chang Ho, Chung-Hao Chu, Tz-Hau Guo
  • Bipolar junction transistor and integrated circuit device
    Patent number: 10290725
    Abstract: A bipolar junction transistor includes a semiconductor substrate, a fin structure, an epitaxial emitter, an epitaxial collector and a gate. The fin structure is disposed on the semiconductor substrate and has a base portion of a first conductivity type, a first recessed portion and a second recessed portion. The epitaxial emitter of a second conductivity type is disposed in the first recessed portion of the fin structure. The epitaxial collector of the second conductivity type is disposed in the second recessed portion of the fin structure. The gate is disposed on the base portion of the fin structure and isolated from the base portion of the fin structure.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Hao Chu, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang
  • Integrated circuit devices with well regions and methods for forming the same
    Patent number: 10269658
    Abstract: A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Mingo Liu
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190109132
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a gate stack, a first doped region, a second doped region, and a buried doped region. The first doped region has a first conductivity type and is located in the substrate at a first side of the gate stack. The second doped region has the first conductivity type and is located in the substrate at a second side of the gate stack. The buried doped region has the first conductivity type and is buried in the substrate, extended from the first doped region to the second doped region, and separated from the gate stack by a distance.
    Type: Application
    Filed: November 26, 2018
    Publication date: April 11, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190096881
    Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.
    Type: Application
    Filed: November 26, 2018
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190006480
    Abstract: A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer, a metal feature, and a semiconductor feature. The metal feature is disposed on the gate dielectric layer. The semiconductor feature is disposed on the gate dielectric layer. The metal feature and the semiconductor feature are stacked on the gate dielectric layer side by side.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Meng-Chang Ho, Chung-Hao Chu, Tz-Hau Guo
  • Semiconductor device and manufacturing method thereof
    Patent number: 10170571
    Abstract: A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer, a metal feature, and a semiconductor feature. The metal feature is disposed on the gate dielectric layer. The semiconductor feature is disposed on the gate dielectric layer. The metal feature and the semiconductor feature are stacked on the gate dielectric layer side by side.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Meng-Chang Ho, Chung-Hao Chu, Tz-Hau Guo
  • Semiconductor device and manufacturing method thereof
    Patent number: 10157916
    Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • FinFET having isolation structure and method of forming the same
    Patent number: 10141429
    Abstract: A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, a first isolation structure over the upper surface of the substrate, and a second isolation structure. The fin structure extends along a first direction and comprising a lower portion and an upper portion. The first isolation structure surrounds the lower portion of the fin structure. The second isolation structure is at least partially embedded in the upper portion of the fin structure.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Fu-Huan Tsai, Feng Yuan
  • FinFET Varactor with Low Threshold Voltage and Method of Making the Same
    Publication number: 20180337173
    Abstract: FinFET varactors having low threshold voltages and methods of making the same are disclosed herein. An exemplary FinFET varactor includes a fin and a gate structure disposed over a portion of the fin, such that the gate structure is disposed between a first source/drain feature and a second source/drain feature that include a first type dopant. The portion of the fin includes the first type dopant and a second type dopant. A dopant concentration of the first type dopant and a dopant concentration of the second type dopant vary from an interface between the fin and the gate structure to a first depth in the fin. The dopant concentration of the first type dopant is greater than the dopant concentration of the second type dopant from a second depth to a third depth in the fin, where the second depth and the third depth are less than the first depth.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Fu-Huan Tsai, Han-Min Tsai, Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang
  • MOS devices with mask layers and methods for forming the same
    Patent number: 10134868
    Abstract: A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chu-Fu Chen, Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20180294261
    Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • BIPOLAR JUNCTION TRANSISTOR AND INTEGRATED CIRCUIT DEVICE
    Publication number: 20180277666
    Abstract: A bipolar junction transistor includes a semiconductor substrate, a fin structure, an epitaxial emitter, an epitaxial collector and a gate. The fin structure is disposed on the semiconductor substrate and has a base portion of a first conductivity type, a first recessed portion and a second recessed portion. The epitaxial emitter of a second conductivity type is disposed in the first recessed portion of the fin structure. The epitaxial collector of the second conductivity type is disposed in the second recessed portion of the fin structure. The gate is disposed on the base portion of the fin structure and isolated from the base portion of the fin structure.
    Type: Application
    Filed: March 22, 2017
    Publication date: September 27, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Hao Chu, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang
  • HIGH-SPEED SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20180277662
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate structure over a fin structure. The method includes forming a hard mask layer over the gate structure. The hard mask layer has a first opening spaced apart from a first side of the gate structure by a first distance and a second opening spaced apart from a second side of the gate structure by a second distance that is different from the first distance. The method also includes removing the fin structure not covered by the hard mask layer. The method further includes forming a first source/drain feature in the fin structure and filling the first opening of the hard mask layer. The method further includes forming a second source/drain feature in the fin structure and filling the second opening of the hard mask layer.
    Type: Application
    Filed: March 24, 2017
    Publication date: September 27, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Victor Chiang LIANG, Chia-Chung CHEN, Chi-Feng HUANG, Shu-Fang FU
  • HVMOS Reliability Evaluation using Bulk Resistances as Indices
    Publication number: 20180277539
    Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
    Type: Application
    Filed: June 1, 2018
    Publication date: September 27, 2018
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Tse-Hua Lu
  • MOS Devices with Mask Layers and Methods for Forming the Same
    Publication number: 20180226488
    Abstract: A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Inventors: Chu-Fu Chen, Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang