A METAL-OXIDE FIELD EFFECT TRANSISTOR HAVING AN OXIDE REGION WITHIN A LIGHTLY DOPED DRAIN REGION
A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. A source region and a drain region are disposed on opposite sides of the gate structure on the semiconductor substrate. A lightly-doped drain region is adjacent to a side of the drain region close to the gate structure, and a lightly-doped source region is adjacent to a side of the source region close to the gate structure. An oxidation region is disposed in the lightly-doped drain region. A trench extends from the surface of the semiconductor substrate to the drain region. A source electrode is disposed on the source region, and the drain electrode has a first portion disposed on the drain region and a second portion disposed in the trench.
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Field of the Invention
The invention relates to a semiconductor device and method for fabricating the same, and in particular to a semiconductor device with a metal-oxide-semiconductor field effect transistor and method for fabricating the same.
Description of the Related Art
In the semiconductor process of a metal-oxide-semiconductor field effect transistor (MOSFET), there are electrons in an electric field because they are attracted by the positive electric potential, and the electrons will gain kinetic energy and become accelerated. For example, when the channel length of the MOSFET decreases, if the applied voltage stays unchanged, the lateral electric field in the channel will increase. As a result, after being accelerated by the lateral electric field, the energy of the electrons will increase greatly. Because the energy of the electrons accelerated by the lateral electric field is greater than that of the electrons in a state of thermal equilibrium, the electrons with more energy may be regarded as hot carriers. Hot carriers may cause impact ionization, particularly in the region where the channel connects to the drain region. When the energy of the hot carriers is greater than the energy barrier between the channel and the gate dielectric layer (Si—SiO2), the ionized electrons/holes impacted by the hot carriers may be injected into the gate electrode and cause a hot carrier injection (HCI) effect. While experiencing the HCI effect, the electrical properties of the device may be unstable, leading to the electrical properties of the device having a decreased reliability level.
In general, with conventional processing, the electric field of the region where the channel connects to the drain region is decreased by a lightly-doped drain being disposed so as to reduce the HCI effect. However, the HCI effect becomes worse as the driving current gets larger due to scaling-down of the size of transistor devices, and so a new method of processing is needed to reduce the HCI effect.
BRIEF SUMMARY OF THE INVENTIONAn embodiment of the invention provides a semiconductor device, comprising a semiconductor substrate. A gate structure is disposed on the semiconductor substrate. A source region and a drain region are disposed on opposite sides of the gate structure on the semiconductor substrate. A lightly doped drain region is adjacent to a side of the drain region close to the gate structure. A lightly doped source region is adjacent to a side of the source region close to the gate structure. An oxide region is disposed in the lightly doped drain region. A trench extends from the surface of the semiconductor substrate into the drain region. A source electrode is disposed on the source region, and a drain electrode has a first portion disposed on the drain region and a second portion disposed in the trench.
An embodiment of the invention provides a method for fabricating a semiconductor device, the method comprising: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; forming a lightly doped source region and a lightly doped drain region on opposite sides of the gate structure on the semiconductor substrate; forming a source region and a drain region adjacent to the lightly doped source region and the lightly doped drain region, respectively; forming an oxide region in the lightly doped drain region; forming a trench extending from the surface of the semiconductor substrate into the drain region; forming a source electrode on the source region; and forming a drain electrode with a first portion disposed on the drain region and a second portion disposed in the trench.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The semiconductor device of the present disclosure is described in detail in the following description. In the following detailed description, for purposes of explanation, numerous specific details and embodiments are set forth in order to provide a thorough understanding of the present disclosure. The specific elements and configurations described in the following detailed description are set forth in order to clearly describe the present disclosure. It will be apparent, however, that the exemplary embodiments set forth herein are merely for the purpose of illustration, and the inventive concept may be embodied in various forms without being limited to those exemplary embodiments. In addition, the drawings of different embodiments may use like and/or corresponding numerals to denote like and/or corresponding elements in order to clearly describe the present disclosure. However, the like and/or corresponding numerals in the drawings of different embodiments do not suggest any correlation between different embodiments. In addition, in this specification, expressions such as “first material layer disposed on/over a second material layer”, may indicate not only the direct contact of the first material layer and the second material layer, but also, a non-contact state with one or more intermediate layers between the first material layer and the second material layer. In the above situation, the first material layer may not directly contact the second material layer.
In addition, in this specification, relative expressions are used. For example, “lower”, “bottom”, “higher” or “top” are used to describe the position of one element relative to another. It should be appreciated that if a device is flipped upside down, an element at a “lower” side will become an element at a “higher” side.
The terms “about” and “substantially” typically mean +/−20% of the stated value, more typically +/−10% of the stated value and even more typically +/−5% of the stated value. The stated value of the present disclosure is an approximate value. When there is no specific description, the stated value includes the meaning of “about” or “substantially”.
Referring to the process flow diagram as shown in
At 102, a gate dielectric layer 204 is formed on a semiconductor substrate 202, as shown in
At 104, a gate electrode layer is formed on the gate dielectric layer 204, wherein the gate electrode layer may include doped polysilicon, metal material and metal silicide. The material of the gate electrode layer may be formed by a CVD process, sputtering process, resistor thermal evaporation process, electron beam (EB) evaporation process, or another suitable deposition method. For example, in an embodiment, amorphous silicon conductive material or polysilicon conductive material is fabricated by an LPCVD process. Subsequently, the gate electrode layer is patterned to form a gate electrode 206 (which is not illustrated in
Subsequently, the photoresist on the gate electrode 206 is removed, in some embodiments, the photoresist may be removed utilizing, e.g., an ashing process, whereby the temperature of the photoresist is raised until the photoresist experiences a thermal decomposition and may be easily removed. However, any other suitable removal process may alternatively be utilized. Once the ashing process has been performed, the structure may be cleaned by a cleaning process in order to assist in the removal of the photoresist. In an embodiment, the cleaning process may include dipping the semiconductor device 200 into an etchant in order to ensure that any remaining portions of the photoresist are removed from the semiconductor device 200 prior to subsequent processing. For example, the semiconductor device 200 may be dipped into an etchant such as HF for between about 10 seconds and about 30 seconds, such as about 20 seconds.
Then, the gate electrode 206 is used as an etching mask, and an etching process is performed to etch the exposed gate dielectric layer 204. In some embodiments, the etching process may be a wet etching process, dry etching process, plasma etching process, reactive ion etching (RIE) process, or a similar process. As a result, a patterned gate dielectric layer 204 and the gate electrode 206 disposed thereon are formed. The patterned gate dielectric layer 204 and the gate electrode 206 disposed thereon may be regarded as a gate structure 208, as shown in
At 104, a lightly-doped drain region 210a and a lightly-doped source region 210b are disposed on opposite sides of the gate structure on the semiconductor substrate, as shown in
At 106, an oxygen ion implantation process 211 is performed on the lightly-doped drain region 210a, as shown in
At 108, a pair of spacers 212 is formed on sidewalls of the gate structure 208, as shown in
At 110, a heavily doped implantation process 213 is performed on the semiconductor substrate 202, as shown in
At 112, an annealing process (not illustrated) is performed to activate the drain region 214a and the source region 214b and to let the oxygen ions form an oxide region, as shown in
At 114, a trench 218 is formed from a surface of the semiconductor substrate 202 and extending into the drain region 214a, as shown in
At 116, a source electrode 220 and a drain electrode 222 are formed, as shown in
As set forth, the oxide region 216 in the lightly-doped drain region 210a of the present invention may bypass the current flowing from the source to the drain. In addition, the first portion 224 of the drain electrode 222 on the drain region 214a and the second portion 226 of the drain electrode 222 in the trench 218 may let the bypass current bypassed by the oxide region 216 in the lightly-doped drain region 210a flow to the first portion 224 and the second portion 226 respectively to achieve the effect of bypassing the current (as the arrow shows in
Although some embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present disclosure. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Although some embodiments of the present disclosure have been described in detail, it is to be understood that the invention is not limited to the disclosed embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. Therefore, it is intended that the specification and examples be considered as exemplary only, with the true scope of the disclosure being indicated by the following claims and their equivalents.
Claims
1. A semiconductor device, comprising:
- a semiconductor substrate;
- a gate structure disposed on the semiconductor substrate;
- a source region and a drain region disposed on opposite sides of the gate structure on the semiconductor substrate;
- a lightly doped drain region adjacent to a side of the drain region adjacent to the gate structure;
- a lightly doped source region adjacent to a side of the source region adjacent to the gate structure;
- an oxide region disposed in the lightly doped drain region;
- a trench extending from a surface of the semiconductor substrate into the drain region;
- a source electrode disposed on the source region; and
- a drain electrode having a first portion disposed on the drain region and a second portion disposed in the trench,
- wherein a bottom surface of the second portion of the drain electrode is lower than a bottom surface of the lightly doped drain region.
2. The semiconductor device as claimed in claim 1, wherein the oxide region is fully enclosed by the lightly doped drain region.
3. (canceled)
4. The semiconductor device as claimed in claim 1, wherein a top surface of the second portion of the drain electrode is lower than a bottom surface of the oxide region, but higher than a bottom surface of the lightly doped drain region.
5. The semiconductor device as claimed in claim 1, wherein the gate structure further comprises:
- a gate dielectric layer disposed on the semiconductor substrate; and
- a gate electrode disposed on the gate dielectric layer.
6. The semiconductor device as claimed in claim 1, further comprising:
- a pair of spacers disposed on sidewalls of the gate structure, and wherein the oxide region is correspondingly disposed beneath one of the pair of spacers.
7. A method for fabricating the semiconductor device of claim 1, comprising:
- providing the semiconductor substrate;
- forming the gate structure on the semiconductor substrate;
- forming the lightly doped source region and the lightly doped drain region on opposite sides of the gate structure on the semiconductor substrate;
- forming the source region and the drain region adjacent to the lightly doped source region and the lightly doped drain region respectively;
- forming the oxide region in the lightly doped drain region;
- forming the trench extending from the surface of the semiconductor substrate into the drain region;
- forming the source electrode on the source region; and
- forming the drain electrode with the first portion disposed on the drain region and a second portion disposed in the trench.
8. The method as claimed in claim 7, wherein the oxide region is fully enclosed by the lightly doped drain region.
9. (canceled)
10. The method as claimed in claim 7, wherein a top surface of the second portion of the drain electrode is lower than a bottom surface of the oxide region, but higher than a bottom surface of the lightly doped drain region.
11. The method as claimed in claim 7, wherein forming the gate structure further comprises:
- forming a gate dielectric layer on the semiconductor substrate; and
- forming a gate electrode on the gate dielectric layer.
12. The method as claimed in claim 7, further comprising:
- forming a pair of spacers on sidewalls of the gate structure, wherein the oxide region is correspondingly disposed beneath one of the pair of spacers.
13. The method as claimed in claim 7, wherein forming the oxide region further comprises:
- before forming the source region and the drain region, performing an oxygen ion implantation process to the lightly doped drain region; and
- after forming the source region and the drain region, performing an annealing process so that oxygen ions in the lightly doped drain region form the oxide region.
Type: Application
Filed: Oct 22, 2015
Publication Date: Apr 27, 2017
Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION (Hsinchu)
Inventors: Chih-Hung LIN (Taichung City), Chia-Hao LEE (New Taipei City), Chih-Cherng LIAO (Jhudong Township)
Application Number: 14/920,426