Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether rate of increase of saturating read current is less than first threshold value; when rate of increase of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether rate of increase of saturating read current is less than first threshold value; finishing the method when rate of increase of saturating read current is less than first threshold value and saturating read current reaches target current value.

Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.

Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.

Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

Abstract: An electronic device including a bracket and an antenna is provided. The bracket includes first, second, third, and fourth surfaces. The antenna includes a radiator. The radiator includes first, second, third, and fourth portions. The first portion is located on the first surface and includes connected first and second sections. The second portion is located on the second surface and includes third, fourth, fifth, and sixth sections. The third section, the fourth section, and the fifth sections are bent and connected to form a U shape. The third portion is located on the third surface and is connected to the second section and the fourth section. The fourth portion is located on the fourth surface and is connected to the fifth section, the sixth section, and the third portion. The radiator is adapted to resonate at a low frequency band and a first high frequency band.

Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

Abstract: A micro LED and a manufacturing method thereof are provided. The micro LED includes a first semiconductor layer, an active layer, and a second semiconductor layer that are successively stacked together. The first semiconductor layer and the second semiconductor layer are of different types. The active layer includes a first quantum well layer and a second quantum well layer stacked together. The second quantum well layer and the second semiconductor layer form a nanoring. The first quantum well layer is configured to emit light of a first color. The second quantum well layer forming a sidewall of the nanoring is configured to emit light of a second color different from the first color. The first semiconductor layer is electrically coupled to a first electrode, and the second semiconductor layer is electrically coupled to a second electrode. A manufacturing method for a micro LED is provided.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A pharmaceutical composition containing a mixed polymeric micelle and a drug enclosed in the micelle, in which the mixed polymeric micelle, 1 to 1000 nm in size, includes an amphiphilic block copolymer and a lipopolymer. Also disclosed are preparation of the pharmaceutical composition and use thereof for treating cancer.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: The present application provides an epitaxial wafer of a red light-emitting diode, and a preparation method therefor, by designing an n-type semiconductor layer as a gradient layer with the content of an aluminum element gradually increasing along a growth direction of the epitaxial wafer and the content of an indium element gradually decreasing along a stacking direction of the epitaxial wafer, and a constant layer with the content of an aluminum element and an indium element not changing along the growth direction of the epitaxial wafer, the potential barrier at the side close to a multi-quantum well layer gradually rises, preventing electrons and holes in the multi-well quantum layer for radiative recombination from moving to the outside of the MQW region, confining the holes and electrons to have a radiative recombination in the MQW and reducing non-radiative recombination, and also facilitating the flowing of electrons in the n-layer to the MQW region.

Abstract: A light emitting diode (LED) and a light purification method therefor are provided, which belong to the technical field of LED. The LED includes an epitaxial structure and a light purification layer plated on the epitaxial structure. The light purification layer includes a first reflection layer and defines multiple light-exiting holes. The first reflection layer is plated on the epitaxial structure. The multiple light-exiting holes each extend through the first reflection layer and have an aperture which is N times a preset wavelength of an exit light, N being an integer and N?1.

Abstract: Provided are a micro light-emitting diode chip and a manufacturing method therefor, and a display device. The micro light-emitting diode chip comprises: a first-type semiconductor layer, a light-emitting layer and a second-type semiconductor layer which are sequentially stacked, wherein the light-emitting layer is located between the first-type semiconductor layer and the second-type semiconductor layer; and a reflective layer provided at a light-emitting side of the light-emitting layer, wherein the reflective layer is configured to block light emitted by the light-emitting layer to an edge of the micro light-emitting diode chip.

Abstract: A light emitting diode (LED) and a light purification method therefor are provided, which belong to the technical field of LED. The LED includes an epitaxial structure and a light purification layer plated on the epitaxial structure. The light purification layer includes a first reflection layer and defines multiple light-exiting holes. The first reflection layer is plated on the epitaxial structure. The multiple light-exiting holes each extend through the first reflection layer and have an aperture which is N times a preset wavelength of an exit light, N being an integer and N?1.

Abstract: A light emitting diode (LED) is provided in the disclosure. The LED includes a first contact electrode, a first semiconductor layer, a light emitting layer, a second semiconductor layer, a current diffusion layer and a second contact electrode that are successively stacked. Multiple micro-structures extend through the light emitting layer and the second semiconductor layer in a stacking direction of the light emitting layer and the second semiconductor layer, where the multiple micro-structures each defines a borehole space. The borehole space has opposite ends which are respectively closed by the first semiconductor layer and the current diffusion layer. Quantum dots are filled in the borehole space of the multiple micro-structures. Lights of corresponding colors are emitted by exciting corresponding quantum dots with a part of blue lights emitted by the micro-structures.

Abstract: This disclosure relates to a superlattice structure, an LED epitaxial structure, a display device, and a method for manufacturing the LED epitaxial structure. The superlattice structure includes at least two superlattice units which are grown in stacking layers. Each of the at least two superlattice units includes a first n-type GaN layer, a second n-type GaN layer, a first n-type GaInN layer, and a second n-type GaInN layer which are grown in stacking layers. The first n-type GaN layer has a doping concentration which is constant along a growth direction, the second n-type GaN layer has a doping concentration which gradually increases along the growth direction, the first n-type GaInN layer has a doping concentration which gradually decreases along the growth direction, and the second n-type GaInN layer has a doping concentration which is constant along the growth direction.

Abstract: A micro LED and a manufacturing method thereof are provided. The micro LED includes a first semiconductor layer, an active layer, and a second semiconductor layer that are successively stacked together. The first semiconductor layer and the second semiconductor layer are of different types. The active layer includes a first quantum well layer and a second quantum well layer stacked together. The second quantum well layer and the second semiconductor layer form a nanoring. The first quantum well layer is configured to emit light of a first color. The second quantum well layer forming a sidewall of the nanoring is configured to emit light of a second color different from the first color. The first semiconductor layer is electrically coupled to a first electrode, and the second semiconductor layer is electrically coupled to a second electrode. A manufacturing method for a micro LED is provided.