Abstract: An LED comprises a substrate, a buffer layer, an epitaxial layer and a conductive layer. The epitaxial layer comprises a first N-type epitaxial layer, a second N-type epitaxial layer, and a blocking layer with patterned grooves sandwiched between the first and second N-type epitaxial layers. The first and second N-type epitaxial layers make contact each other via the patterned grooves. Therefore, the LED enjoys a uniform current distribution and a larger light emitting area. A manufacturing method for the LED is also provided.

Abstract: An LED chip includes a substrate, a first type semiconductor layer, a light-emitting layer, a second type semiconductor layer, a first electrode and a second electrode formed on the substrate in sequence. A surface of the first type semiconductor layer away from the substrate comprises an exposed first area and a second area covered by the light-emitting layer. The first electrode is formed on the exposed first area of the substrate. A number of recesses are defined in the second area of the surface of the first type semiconductor layer. The recesses are spaced apart from each other and arranged in sequence in a direction away from the first electrode; depths of the recesses gradually decrease following an increase of a distance between the recesses and the first electrode. The second electrode is formed on the second type semiconductor layer.

Abstract: A light emitting diode includes a substrate, an N-type semiconductor layer arranged on the substrate, an active layer, and a P-type semiconductor layer. The active layer includes a first barrier layer, a second barrier layer, and a quantum well structure layer arranged between the first and second barrier layers. The quantum well structure layer includes an InN layer, a GaN layer and an InGaN layer arranged on the first barrier layer in sequence. The InN layer has an upper surface connected to the GaN layer. The upper surface is rough. The InGaN layer has a concentration of In atoms in some regions of the InGaN layer which is higher that that in other regions thereof. The P-type semiconductor layer is arranged on the second barrier layer.

Abstract: A method includes establishing an initial shot layout in which a number of shots are arranged in vertically aligned columns and horizontally aligned rows to cover a semiconductor wafer. At least one of a row of shots or a column of shots is shifted relative to an adjacent row or column of shots to establish at least one additional shot layout that differs from the initial shot layout in that shots in the at least one shifted row or column of shots are not aligned with the shots in the adjacent row or column of shots with which they were aligned in the initial shot layout. One of the initial shot layout and the at least one additional shot layout is selected as a final shot layout. The wafer is exposed to light using the final shot layout.

Abstract: A method for fabricating a semiconductor lighting chip includes steps of: providing a substrate with a first block layer dividing an upper surface of the substrate into a plurality of epitaxial regions; forming a first semiconductor layer on the epitaxial regions; forming a second block layer partly covering the first semiconductor layer; forming a lighting structure on an uncovered portion of the first semiconductor layer; removing the first and the second block layers thereby defining clearances at the bottom surfaces of the first semiconductor layer and the lighting structure; and permeating etching solution into the first and second clearances to etch the first semiconductor layer and the lighting structure, thereby to form each of the first semiconductor layer and the lighting structure with an inverted frustum-shaped structure.

Abstract: A light emitting diode chip includes an electrically conductive substrate, a reflecting layer disposed on the substrate, a semiconductor structure formed on the reflecting layer, an electrode disposed on the semiconductor structure, and a plurality of slots extending through the semiconductor structure. The semiconductor structure includes a P-type semiconductor layer formed on the reflecting layer, a light-emitting layer formed on the P-type semiconductor layer, and an N-type semiconductor layer formed on the light-emitting layer. A current diffusing region is defined in the semiconductor structure and around the electrode. The slots are located outside the current diffusing region.

Abstract: A method for manufacturing light emitting chips includes steps of: providing a substrate having a plurality of separate epitaxy islands thereon, wherein the epitaxy islands are spaced from each other by channels; filling the channels with an insulation material; sequentially forming a reflective layer, a transition layer and a base on the insulation material and the epitaxy islands; removing the substrate and the insulation material to expose the channels; and cutting the reflective layer, the transition layer and the base to form a plurality of individual chips along the channels.

Abstract: A method for making a solid state semiconductor device includes: providing a substrate; forming a buffer layer on the substrate; forming a first epitaxial layer on the buffer layer; forming a surface-textured second epitaxial layer on the first epitaxial layer by chemical vapor deposition; and forming a solid state stacked layer structure having a PN-junction type light-emitting part on a textured surface of the second epitaxial layer.

Abstract: A semiconductor light-emitting structure includes a silicon substrate, a distributed Bragg reflector, a semiconductor structures layer and an epitaxy connecting layer. The silicon substrate has a top surface. The distributed Bragg reflector is formed on the top surface of the silicon substrate. The semiconductor structures layer is configured for emitting light. The epitaxy connecting layer is placed between the distributed Bragg reflector and the semiconductor structures layer. Grooves extend from the semiconductor structures layer through the epitaxy connecting layer and the distributed Bragg reflector to reach the semiconductor structures layer.

Abstract: An epitaxy substrate for growing a plurality of semiconductor epitaxial layers thereon, includes a plurality of growth areas and a plurality of protected areas. The growth areas are provided for growing the semiconductor epitaxial layers thereon. The growth areas and the protected areas are alternating. A thickness of the growth areas is less than ? of a thickness H of the protected areas.

Abstract: A light emitting diode comprises a substrate, a buffer layer, a semiconductor layer and a semiconductor light emitting layer. The buffer layer is disposed on the substrate. The semiconductor layer is disposed on the buffer layer. The semiconductor light emitting layer is disposed on the semiconductor layer. A plurality of voids is defined within the semiconductor layer. Each void encloses air therein. A method for manufacturing the light emitting diode is also provided. Light generated by the semiconductor light emitting layer toward the substrate is reflected by the voids to emit out of the light emitting diode.

Abstract: A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate.

Abstract: A semiconductor structure includes a Si substrate, a supporting layer and a blocking layer formed on the substrate and an epitaxy layer formed on the supporting layer. The supporting layer defines a plurality of grooves therein to receive the blocking layer. The epitaxy layer is grown from the supporting layer. A plurality of slots is defined in the epitaxy layer and over the blocking layer. The epitaxy layer includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer. A method for manufacturing the semiconductor structure is also disclosed.

Abstract: A method for providing a bin ratio forecast at an early stage of integrated circuit device manufacturing processes is disclosed. The method comprises collecting historical data from one or more processed wafer lots; collect measurement data from one or more skew wafer lots; generating an estimated baseline distribution from the collected historical data and collected measurement data; generating an estimated performance distribution based on one or more specified parameters and the generated estimated baseline distribution; determining a bin ratio forecast by applying a bin definition and a yield degradation factor estimation to the generated estimated performance distribution; determining one or more production targets based on the bin ratio forecast; and processing one or more wafers based on the one or more determined production targets.

Abstract: A light emitting element package includes a substrate, at least two light emitting element modules and an encapsulation member. The substrate includes a circuit layer. The circuit layer includes a plurality of solder pads. The at least two light emitting element modules are mounted on the substrate. Each of the at least two light emitting element modules includes a plurality of light emitting elements. Each light emitting element of the at least two light emitting element modules is electrically coupled to neighboring light emitting element in serial through the solder pads. The at least two light emitting element modules are reversely arranged. The encapsulation member is configured to encapsulate the at least two light emitting element modules on the substrate.

Abstract: A light emitting diode includes a substrate, a buffer layer on the substrate, a patterned layer having a first reflective index on the buffer layer, a semiconductor layer having a second reflective index on the patterned layer, and an illumination structure on the semiconductor layer. A method for manufacturing the light emitting diode is also provided.

Abstract: A light emitting element includes a substrate, a GaN layer formed on the substrate, a first low refractive index semiconductor layer formed on the GaN layer, and a lighting structure having a high refractive index formed on the first low refractive index semiconductor layer. A second low refractive index semiconductor layer is embedded in the first low refractive index semiconductor layer. The first low refractive index semiconductor layer and the GaN layer exhibit a lattice mismatch therebetween.

Abstract: A manufacturing method of a platinum complex is mixing chloroplatinic acid and a chelating agent with a solvent, wherein [PtCl6]2? ions of the chloroplatinic acid is reacted with the chelating agent to form a platinum complex Pt[R]2+, wherein the chelating agent(R) is selected from ethylenediamine , 1,10-phenanthroline, 2,2?-Bipyridine, diethylenetriamine, triethylenetetraamine, phenanthroline, or bipyridine. Moreover, a method for producing a platinum catalyst on supports is mixing the chloroplatinic acid, a chelating agent and supports with a slovent to form a platinum complex, which is incorporated onto the supports. Following, a reduction step and a drying step are processed to get the platinum catalyst on the supports.

Abstract: A manufacturing method of an iron complex is mixing ferric chloride and at least one chelating agent with a solvent, wherein Fe3+ ions of ferric chloride is reacted with the at least one chelating agent to form an iron complex Fe[R1]a[R2]b[H2O]c3+ or Fe[R1]a[H2O]c3+, wherein the at least one chelating agent is selected from a group including ethylenediamine, 1,10-phenanthroline, 2,2?-Bipyridine, diethylenetriamine, triethylenetetraamine, phenanthroline, or bipyridine. Moreover, a method for producing an iron oxide catalyst is mixing ferric chloride, at least one chelating agent and the support with a slovent to form an iron complex, which is incorporated with the support. Following, a drying step and a heat treatment step are processed to get the iron oxide catalyst.

Abstract: A method for providing a bin ratio forecast at an early stage of integrated circuit device manufacturing processes is disclosed. The method comprises collecting historical data from one or more processed wafer lots; collect measurement data from one or more skew wafer lots; generating an estimated baseline distribution from the collected historical data and collected measurement data; generating an estimated performance distribution based on one or more specified parameters and the generated estimated baseline distribution; determining a bin ratio forecast by applying a bin definition and a yield degradation factor estimation to the generated estimated performance distribution; determining one or more production targets based on the bin ratio forecast; and processing one or more wafers based on the one or more determined production targets.