Patents by Inventor Chia-Jung Hsu

Chia-Jung Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210174400
    Abstract: A device for providing a food advertisement based on food flavors to market a food product, including a carrier and a plurality of color patches provided on the carrier and combined into a color pattern. The color patches are generated according to a colorimetric sensor array sensing the food product, and the colorimetric sensor array includes a plurality of sensing materials for sensing the food product. The sensing materials respectively react with at least one metabolic molecule of the food to change from an initial color to an indication color corresponding to the color patches respectively, so that the color pattern is visually associated with flavor information of the food product correspondingly.
    Type: Application
    Filed: November 18, 2020
    Publication date: June 10, 2021
    Inventors: Ching-Tung HSU, Chun-Wei SHIH, Chia-Hung LI, Chao-Chieh LIN, Yuan-Shin HUANG, Chun-Hsien TSAI, Chun-Jung TSAI
  • Publication number: 20210156791
    Abstract: A residual toxicant detection device for testing residual toxicant in an aqueous solution is disclosed, which includes a first space cavity, a second space cavity, a connecting frame and a sensing cavity. The first space cavity includes a light source and a lens. The second space cavity includes a photo sensor and a circuit module. The connecting frame is configured to connect the first space cavity and the second space cavity. The sensing cavity for receiving an aqueous solution is formed between the first space cavity and the second space cavity and at one side of the connecting frame. The light source emits a light with a wavelength range. The photo sensor receives the sensing signal of the light passing through the sensing cavity. The circuit module is configured to calculate the absorbance and the variation in absorbance of the residual toxicants in the aqueous solution.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 27, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Hao HSU, Jui-Hung TSAI, Ying-Hao WANG, Chia-Jung CHANG
  • Publication number: 20210149462
    Abstract: An electronic device includes a first main body, a second main body, a pivoting mechanism, and a heat dissipation module. The second main body includes a first housing, a second housing, and a cover plate. The pivoting mechanism is pivotally connected between the first main body and the second main body. Two sides of the cover plate are pivotally connected to the second housing and the pivoting mechanism respectively. The heat dissipation module is disposed in the second main body and includes at least one elastic member. The elastic member is fixed between the first housing and the cover plate. In response to that the first main body is in unfolded position relative to the second main body through the pivoting mechanism, the pivoting mechanism drives the cover plate to be located between an open position relative to the second housing, so that the elastic member is stretched.
    Type: Application
    Filed: February 4, 2020
    Publication date: May 20, 2021
    Applicant: Wistron Corporation
    Inventors: Huan-Chun Wu, Chao-Yu Li, Chin-Jung Li, Chia-Jui Hsu
  • Publication number: 20210148897
    Abstract: The present invention provides a chemical sensor comprising a substrate, a first colorimetric sensor array exposed and arranged in a first accommodating space of the substrate and a second colorimetric sensor array arranged in a second accommodating space of the substrate. The second accommodating space is covered with an isolating layer to isolates liquid molecules but allows gas molecules to pass through. The first colorimetric sensor array changes from a first initial color to a first indicating color according to a volatile part and a non-volatile part of an analyte, and the second colorimetric sensor array changes from a second initial color to a second indicating color according to the volatile part of the analyte, so that information of the volatile part and the non-volatile part of the analyte can be obtained simultaneously.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 20, 2021
    Inventors: Ching-Tung HSU, Chao-Chieh LIN, Yuan-Shin HUANG, Chun-Wei SHIH, Chia-Hung LI, Chun-Hsien TSAI, Chun-Jung TSAI
  • Publication number: 20210150168
    Abstract: The present invention provides a product label with a colorimetric sensor array and a code, and the system and the method of the present invention are mainly that the product label is attached to a fresh food, so that at least one sensing material of the colorimetric sensor array undergoes a chemical reaction with at least one metabolic molecule of the fresh food to change from an initial color to an indicating color. The present invention, by obtaining an image comprising an appearance, the code and the indicating color of the fresh food through an image acquisition device, also provides an instant information associated with the fresh food by a processing device according to a comparison result of the image and a database.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 20, 2021
    Inventors: Ching-Tung HSU, Chao-Chieh LIN, Yuan-Shin HUANG, Chun-Wei SHIH, Chia-Hung LI, Chun-Hsien TSAI, Chun-Jung TSAI
  • Patent number: 11011533
    Abstract: A memory structure including a first select transistor, a first floating gate transistor, a second select transistor, a second floating gate transistor, and a seventh doped region is provided. The first select transistor includes a select gate, a first doped region, and a second doped region. The first floating gate transistor includes a floating gate, the second doped region, and a third doped region. The second select transistor includes the select gate, a fourth doped region, and a fifth doped region. The second floating gate transistor includes the floating gate, the fifth doped region, and a sixth doped region. A gate width of the floating gate in the second floating gate transistor is greater than a gate width of the floating gate in the first floating gate transistor. The floating gate covers at least a portion of the seventh doped region.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 18, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Chia-Jung Hsu, Wein-Town Sun
  • Patent number: 11010521
    Abstract: A method of detecting the relations between the pins of a circuit and a computer program product thereof are provided. The method includes: retrieving a circuit description file describing a circuit; retrieving at least one data pin and at least one clock pin of the circuit; converting the circuit to a cell level; and tracing the circuit in the cell level to identify multiple flip-flops coupled to the clock pin; tracing the circuit in the cell level to identify a target flip-flop coupled to the data pin; and determining whether the data pin is related to the clock pin according to the data signal and the clock signal of the target flip-flop.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: May 18, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chia-Ling Hsu, Ting-Hsiung Wang, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao
  • Publication number: 20210124864
    Abstract: A power rail design method is disclosed that includes the steps outlined below. A plurality of power rails and a plurality of power domains corresponding thereto in an integrated circuit design file are identified. A design rule check for a plurality of circuit units in the integrated circuit design file is performed to retrieve a plurality of non-violating circuit regions that correspond to the power rails in each of the power domains. The power rails corresponding to at least part of the plurality of non-violating circuit regions in the integrated circuit design file are widened to occupy at least part of the non-violating circuit regions for the plurality of power rails.
    Type: Application
    Filed: October 22, 2020
    Publication date: April 29, 2021
    Inventors: Cheng-Chen HUANG, Yun-Ru WU, Hsin-Chang LIN, Shu-Yi KAO, Chih-Chan CHEN, Chia-Jung HSU, Li-Yi LIN
  • Patent number: 10991810
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate, forming a polymer block on a corner between the gate structure and the substrate, performing an oxidation process to form a first seal layer on sidewalls of the gate structure, and forming a source/drain region adjacent to two sides of the gate structure. Preferably, the polymer block includes fluorine, bromide, or silicon.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 27, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Tsuo-Wen Lu, Chia-Ming Kuo, Po-Jen Chuang, Chi-Mao Hsu
  • Publication number: 20210118750
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Application
    Filed: December 27, 2020
    Publication date: April 22, 2021
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Patent number: 10985264
    Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: April 20, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Patent number: 10971397
    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. The substrate includes a pixel region having a first conductive region and a logic region having a second conductive region. A dielectric layer is formed on the substrate to cover the first conductive region. A first contact opening is formed in the dielectric layer to expose the first conductive region. A doped polysilicon layer is sequentially formed in the first contact opening. A first metal silicide layer is formed on the doped polysilicon layer. A second contact opening is formed in the dielectric layer to expose the second conductive region. A barrier layer and a metal layer are respectively formed in the first contact opening and the second contact opening.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 6, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20210050456
    Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.
    Type: Application
    Filed: September 16, 2019
    Publication date: February 18, 2021
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Publication number: 20210050255
    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. The substrate includes a pixel region having a first conductive region and a logic region having a second conductive region. A dielectric layer is formed on the substrate to cover the first conductive region. A first contact opening is formed in the dielectric layer to expose the first conductive region. A doped polysilicon layer is sequentially formed in the first contact opening. A first metal silicide layer is formed on the doped polysilicon layer. A second contact opening is formed in the dielectric layer to expose the second conductive region. A barrier layer and a metal layer are respectively formed in the first contact opening and the second contact opening.
    Type: Application
    Filed: September 12, 2019
    Publication date: February 18, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20200411329
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Application
    Filed: September 12, 2020
    Publication date: December 31, 2020
    Inventors: TUNG-KAI CHEN, CHING-HSIANG TSAI, KAO-FENG LIAO, CHIH-CHIEH CHANG, CHUN-HAO KUNG, FANG-I CHIH, HSIN-YING HO, CHIA-JUNG HSU, HUI-CHI HUANG, KEI-WEI CHEN
  • Publication number: 20200365722
    Abstract: A memory device includes a well, a first gate layer, a second gate layer, a doped region, a blocking layer and an alignment layer. The first gate layer is formed on the well. The second gate layer is formed on the well. The doped region is formed within the well and located between the first gate layer and the second gate layer. The blocking layer is formed to cover the first gate layer, the first doped region and a part of the second gate layer and used to block electrons from excessively escaping. The alignment layer is formed on the blocking layer and above the first gate layer, the doped region and the part of the second gate layer. The alignment layer is thinner than the blocking layer, and the alignment layer is thinner than the first gate layer and the second gate layer.
    Type: Application
    Filed: May 12, 2020
    Publication date: November 19, 2020
    Inventors: Chia-Jung Hsu, Wei-Ren Chen, Wein-Town Sun
  • Patent number: 10797064
    Abstract: A non-volatile memory cell includes a floating-gate transistor, a select transistor, and a coupling structure. The floating-gate transistor is deposited in a P-well and includes a gate terminal coupled to a floating gate which is a first polysilicon layer, a drain terminal coupled to a bit line, and a source terminal coupled to a first node. The select transistor is deposited in the P-well and includes a gate terminal coupled to a select gate which is coupled to a word line, a drain terminal coupled to the first node, and a source terminal coupled to the source line. The floating-gate transistor and the select transistor are N-type transistors. The coupling structure is formed by extending the first polysilicon layer to overlap a control gate, in which the control gate is a P-type doped region in an N-well and the control gate is coupled to a control line.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: October 6, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chia-Jung Hsu
  • Patent number: 10790187
    Abstract: The disclosure relates to a cleaning composition that aids in the removal of post-etch residues and aluminum-containing material, e.g., aluminum oxide, in the production of semiconductors that utilize an aluminum-containing etch stop layer. The compositions have a high selectivity for post-etch residue and aluminum-containing materials relative to low-k dielectric materials, cobalt-containing materials and other metals on the microelectronic device.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: September 29, 2020
    Assignee: ENTEGRIS, INC.
    Inventors: Emanuel I. Cooper, Makonnen Payne, WonLae Kim, Eric Hong, Sheng-Hung Tu, Chieh Ju Wang, Chia-Jung Hsu
  • Publication number: 20200295160
    Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.
    Type: Application
    Filed: April 9, 2019
    Publication date: September 17, 2020
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Patent number: 10777423
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Kai Chen, Ching-Hsiang Tsai, Kao-Feng Liao, Chih-Chieh Chang, Chun-Hao Kung, Fang-I Chih, Hsin-Ying Ho, Chia-Jung Hsu, Hui-Chi Huang, Kei-Wei Chen