Abstract: Semi-aqueous compositions useful for the selective removal of titanium nitride and/or photoresist etch residue materials relative to metal conducting, e.g., tungsten and copper, and insulating materials from a microelectronic device having same thereon. The semi-aqueous compositions contain at least one oxidant, at least one etchant, and at least one organic solvent, may contain various corrosion inhibitors to ensure selectivity.

Abstract: Compositions useful for the selective removal of titanium nitride and/or photoresist etch residue materials relative to insulating materials from a microelectronic device having same thereon. The removal compositions contain at least one oxidant, one etchant, and one activator to enhance the etch rate of titanium nitride.

Abstract: A wafer polishing apparatus is described herein. The wafer polishing apparatus includes a polish module configured to apply air pressure to a first surface of a wafer while performing a polishing process on a second surface of the wafer. In some implementations, the polish module is further configured to perform a cleaning process and/or a drying process on the second surface of the wafer, such that the same wafer polishing apparatus is configured to perform the polishing process, the cleaning process, and/or the drying process. In some implementations, the polishing module is further configured to air seal edges of the wafer during the polishing process, the cleaning process, and/or the drying process.

Abstract: A memory structure including a first select transistor, a first floating gate transistor, a second select transistor, a second floating gate transistor, and a seventh doped region is provided. The first select transistor includes a select gate, a first doped region, and a second doped region. The first floating gate transistor includes a floating gate, the second doped region, and a third doped region. The second select transistor includes the select gate, a fourth doped region, and a fifth doped region. The second floating gate transistor includes the floating gate, the fifth doped region, and a sixth doped region. A gate width of the floating gate in the second floating gate transistor is greater than a gate width of the floating gate in the first floating gate transistor. The floating gate covers at least a portion of the seventh doped region.

Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.

Abstract: A semiconductor device includes a first fin structure for a first fin field effect transistor (PET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.

Abstract: A method for operating a NVM cell is disclosed. The NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor on an N well. The floating gate transistor includes a floating gate and a floating gate extension capacitively coupled to an erase gate region. The method includes erasing the NVM cell by applying an N well voltage VNW to the N well, wherein VNW>0V; applying a source line voltage VSL to a source doping region of the select transistor, wherein VSL=0V; applying a word line voltage VWL to a select gate of the select transistor, wherein VWL=0V; applying a bit line voltage VBL to a drain doping region of the floating gate transistor, wherein VBL=0V; and applying an erase line voltage VEL to the erase gate region, wherein VEL=VEE.

Abstract: A CMP slurry composition which provides for a high Ge- or SiGe-to-dielectric material selectivity a low rate of Ge or SiGe recess formation includes an oxidant and a germanium removal rate enhancer including at least one of a methylpyridine compound and a methylpyridine derivative compound. In some examples, the slurry composition also includes an etching inhibitor. In some cases, the slurry composition may include an abrasive, a surfactant, an organic complexant, a chelating agent, an organic or inorganic acid, an organic or inorganic base, a corrosion inhibitor, or a buffer. The slurry composition may be distributed onto a surface of a polishing pad disposed on a platen that is configured to rotate. Additionally, a workpiece carrier configured to house a substrate may bring the substrate into contact with the rotating polishing pad and thereby polish the substrate utilizing the slurry composition.

Abstract: A method of performing gamut mapping on an input image for an image output device includes receiving the input image to analyze a color distribution of the input image; determining a protect range corresponding to a first percentage of color codes of the input image and a compression range corresponding to a second percentage of the color codes of the input image based on the color distribution of the input image; and moving at least one of the color codes of the input image outside the protect range of the color codes to the compression range by a compression algorithm to perform gamut mapping on the input image.

Abstract: A nonvolatile memory (NVM) cell includes a semiconductor substrate having a first OD region and a second OD region for forming an erase gate (EG) region. The second OD region is spaced apart from the first OD region and is separated from the first OD region by a trench isolation region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is also disposed on the first OD region. The floating gate transistor includes a floating gate overlying the first OD region. A first floating gate extension continuously extends from the floating gate to the second OD region. The first floating gate extension comprises a P+ doped segment and an N+ doped segment with a P+/N+ interface therebetween.

Abstract: A semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer. The fin structure further includes a first protective layer and a second protective layer made of a different material than the first protective layer. The intermediate layer includes a first semiconductor layer disposed over the base layer, the first protective layer covers at least side walls of the first semiconductor layer and the second protective layer covers at least side walls of the first protective layer.

Abstract: The disclosure relates to a cleaning composition that aids in the removal of post-etch residues and aluminum-containing material, e.g., aluminum oxide, in the production of semiconductors that utilize an aluminum-containing etch stop layer. The compositions have a high selectivity for post-etch residue and aluminum-containing materials relative to low-k dielectric materials, cobalt-containing materials and other metals on the microelectronic device.

Abstract: A method for operating a NVM cell is disclosed. The NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor on an N well. The floating gate transistor includes a floating gate and a floating gate extension capacitively coupled to an erase gate region. The method includes erasing the NVM cell by applying an N well voltage VNW to the N well, wherein VNW>0V; applying a source line voltage VSL to a source doping region of the select transistor, wherein VSL=0V; applying a word line voltage VWL to a select gate of the select transistor, wherein VWL=0V; applying a bit line voltage VBL to a drain doping region of the floating gate transistor, wherein VBL=0V; and applying an erase line voltage VEL to the erase gate region, wherein VEL=VEE .

Abstract: A nonvolatile memory (NVM) cell includes a semiconductor substrate having a first OD region and a second OD region for forming an erase gate (EG) region. The second OD region is spaced apart from the first OD region and is separated from the first OD region by a trench isolation region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is also disposed on the first OD region. The floating gate transistor includes a floating gate overlying the first OD region. A first floating gate extension continuously extends from the floating gate to the second OD region. The first floating gate extension comprises a P+ doped segment and an N+ doped segment with a P+/N+ interface therebetween.

Abstract: A method of performing luminance/brightness adjustment and gamut mapping to high dynamic range images for a display device includes receiving an input image to analyze an image distribution of the input image, generating a scene information of the input image according to the image distribution, and performing luminance/brightness adjustment and gamut mapping to the input image according to the scene information, to generate an output image corresponding to the input image, wherein the scene information is regarded as dynamic metadata of the input image.

Abstract: A CMP slurry composition which provides for a high Ge- or SiGe-to-dielectric material selectivity a low rate of Ge or SiGe recess formation includes an oxidant and a germanium removal rate enhancer including at least one of a methylpyridine compound and a methylpyridine derivative compound. In some examples, the slurry composition also includes an etching inhibitor. In some cases, the slurry composition may include an abrasive, a surfactant, an organic complexant, a chelating agent, an organic or inorganic acid, an organic or inorganic base, a corrosion inhibitor, or a buffer. The slurry composition may be distributed onto a surface of a polishing pad disposed on a platen that is configured to rotate. Additionally, a workpiece carrier configured to house a substrate may bring the substrate into contact with the rotating polishing pad and thereby polish the substrate utilizing the slurry composition.

Abstract: A wafer polishing apparatus is described herein. The wafer polishing apparatus includes a polish module configured to apply air pressure to a first surface of a wafer while performing a polishing process on a second surface of the wafer. In some implementations, the polish module is further configured to perform a cleaning process and/or a drying process on the second surface of the wafer, such that the same wafer polishing apparatus is configured to perform the polishing process, the cleaning process, and/or the drying process. In some implementations, the polishing module is further configured to air seal edges of the wafer during the polishing process, the cleaning process, and/or the drying process.

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, a memory device, and a select transistor. The memory device is located on the substrate. The select transistor is located on the substrate and electrically connected to the memory device. The select transistor includes a select gate, a first dielectric layer, and a second dielectric layer. The select gate is located on the substrate. The first dielectric layer is adjacent to the second dielectric layer, and located between the select gate and the substrate. The first dielectric layer is closer to the memory device than the second dielectric layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

Abstract: A semiconductor device includes a first fin structure for a first fin field effect transistor (FET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.

Abstract: The present disclosure relates to a method of performing a chemical mechanical planarization (CMP) process with a high germanium-to-oxide removal selectivity and a low rate of germanium recess formation. The method is performed by providing a semiconductor substrate having a plurality of germanium compound regions including germanium interspersed between a plurality of oxide regions including an oxide. A slurry is then provided onto the semiconductor substrate. The slurry has an oxidant and an etching inhibitor configured to reduce a removal rate of the germanium relative to the oxide. A CMP process is then performed by bringing a chemical mechanical polishing pad in contact with top surfaces of the plurality of germanium compound regions and the plurality of oxide regions.