Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

Abstract: A memory cell array includes a first bit line, a first word line, a first source line pair and a first memory cell. A select terminal of the first memory cell is connected with the first word line. A first control terminal of the first memory cell is connected with a first source line of the first source line pair. A second control terminal of the first memory cell is connected with a second source line of the first source line pair. A third control terminal of the first memory cell is connected with the first bit line.

Abstract: A CMP slurry composition which provides for a high Ge- or SiGe-to-dielectric material selectivity a low rate of Ge or SiGe recess formation includes an oxidant and a germanium removal rate enhancer including at least one of a methylpyridine compound and a methylpyridine derivative compound. In some examples, the slurry composition also includes an etching inhibitor. In some cases, the slurry composition may include an abrasive, a surfactant, an organic complexant, a chelating agent, an organic or inorganic acid, an organic or inorganic base, a corrosion inhibitor, or a buffer. The slurry composition may be distributed onto a surface of a polishing pad disposed on a platen that is configured to rotate. Additionally, a workpiece carrier configured to house a substrate may bring the substrate into contact with the rotating polishing pad and thereby polish the substrate utilizing the slurry composition.

Abstract: Semi-aqueous compositions useful for the selective removal of titanium nitride and/or photoresist etch residue materials relative to metal conducting, e.g., tungsten and copper, and insulating materials from a microelectronic device having same thereon. The semi-aqueous compositions contain at least one oxidant, at least one etchant, and at least one organic solvent, may contain various corrosion inhibitors to ensure selectivity.

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, a memory device, and a select transistor. The memory device is located on the substrate. The select transistor is located on the substrate and electrically connected to the memory device. The select transistor includes a select gate, a first dielectric layer, and a second dielectric layer. The select gate is located on the substrate. The first dielectric layer is adjacent to the second dielectric layer, and located between the select gate and the substrate. The first dielectric layer is closer to the memory device than the second dielectric layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

Abstract: A method of accessing an on-chip read only memory (ROM) includes dividing a frequency of a system clock by a specific divisor, in order to generate a ROM clock; combining a specific number of adjacent addresses into a combined address, wherein the specific number is determined according to the specific divisor; inserting a first stall signal into a real output data, wherein a length of the first stall signal is determined in order to meet a timing requirement for accessing the on-chip ROM; generating an output data of the on-chip ROM according to the combined address, wherein a width of the output data is extended by a specific multiple which is determined according to the specific number; and generating a first delay corresponding to the length of the first stall signal in the address.

Abstract: The present disclosure relates to a chemical mechanical polishing (CMP) slurry composition that provides for a high metal to dielectric material selectivity along with a low rate of metal recess formation. In some embodiments, the disclosed slurry composition has an oxidant and an etching inhibitor. The oxidant has a compound with one or more oxygen molecules. The etching inhibitor has a nitrogen-oxide compound. The etching inhibitor reduces the rate of metal and dielectric material (e.g., oxide) removal, but does so in a manner that reduces the rate of dielectric material removal by a larger amount, so as to provide the slurry composition with a high metal (e.g., germanium) to dielectric material removal selectivity and with a low rate of metal recess formation.

Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

Abstract: A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes to planarize the formed gate structure using a CMP tool. An in situ gate etching process is performed in a CMP cleaner of the CMP tool to form a gate recess. A contact etch stop layer (CESL) can then be deposited in the formed gate recess and one or more CMP processes performed to planarize the CESL.

Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

Abstract: A storage device protection system including a protection control unit, a detection unit, an account/password input unit, an ID acquiring unit, and an encryption unit is provided. The detection unit determines whether a storage device and a key storage device are both coupled to a host. The account/password input unit receives an administrator ID and an administrator password. The ID acquiring unit obtains IDs of the storage device and the key storage device. The encryption unit encrypts the administrator ID, the administrator password, and the IDs of the storage device and the key storage device into encryption data. The protection control unit stores the encryption data into the key storage device and sets an access mode of the storage device as a protection status according to the administrator ID and the administrator password. Thereby, the storage device can be effectively unlocked by using the key storage device.

Abstract: A method of accessing an on-chip read only memory (ROM) includes dividing a frequency of a system clock by a specific divisor, in order to generate a ROM clock; combining a specific number of adjacent addresses into a combined address, wherein the specific number is determined according to the specific divisor; inserting a first stall signal into a real output data, wherein a length of the first stall signal is determined in order to meet a timing requirement for accessing the on-chip ROM; generating an output data of the on-chip ROM according to the combined address, wherein a width of the output data is extended by a specific multiple which is determined according to the specific number; and generating a first delay corresponding to the length of the first stall signal in the address.

Abstract: A flash memory includes a program voltage generator, plural memory units, a current limiter, and a multi-bit program control unit. The program voltage generator is used for providing a constant program voltage during a detecting cycle and providing a dynamically-adjustable program voltage during a program cycle. The plural memory units output plural drain currents and plural data line voltages to plural data lines. The current limiter is used for receiving a reference current and a reference voltage, thereby controlling the plural drain currents. During the detecting cycle, a specified data line voltage of the plural data line voltages with the minimum voltage level is detected by the multi-bit program control unit. During the program cycle, the specified data line voltage is used as a feedback voltage, and the dynamically-adjustable program voltage is generated by the program voltage generator according to the feedback voltage.

Abstract: A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes to planarize the formed gate structure using a CMP tool. An in situ gate etching process is performed in a CMP cleaner of the CMP tool to form a gate recess. A contact etch stop layer (CESL) can then be deposited in the formed gate recess and one or more CMP processes performed to planarize the CESL.

Abstract: A flash memory includes a program voltage generator, plural memory units, a current limiter, and a multi-bit program control unit. The program voltage generator is used for providing a constant program voltage during a detecting cycle and providing a dynamically-adjustable program voltage during a program cycle. The plural memory units output plural drain currents and plural data line voltages to plural data lines. The current limiter is used for receiving a reference current and a reference voltage, thereby controlling the plural drain currents. During the detecting cycle, a specified data line voltage of the plural data line voltages with the minimum voltage level is detected by the multi-bit program control unit. During the program cycle, the specified data line voltage is used as a feedback voltage, and the dynamically-adjustable program voltage is generated by the program voltage generator according to the feedback voltage.

Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

Abstract: A data protecting method for a rewritable non-volatile memory module having a first storage area and a second storage area and a memory controller and a memory storage device using the same are provided. The method includes providing default configuration information in response to a boot command from a host system, wherein the host system cannot recognize the second storage area according to the default configuration information. The method also includes requesting the host system to re-boot when a user identification code and a user password receiving from the host system pass an authentication procedure, and providing first configuration information to the host system after re-booting the host system. The host system can recognize the second storage area according to the first configuration information. Accordingly, the method can effectively protect data stored in the rewritable non-volatile memory module.

Abstract: A data protecting method for a rewritable non-volatile memory module having a first storage area and a second storage area and a memory controller and a memory storage device using the same are provided. The method includes providing default configuration information in response to a boot command from a host system, wherein the host system cannot recognize the second storage area according to the default configuration information. The method also includes requesting the host system to re-boot when a user identification code and a user password receiving from the host system pass an authentication procedure, and providing first configuration information to the host system after re-booting the host system. The host system can recognize the second storage area according to the first configuration information. Accordingly, the method can effectively protect data stored in the rewritable non-volatile memory module.

Abstract: A storage device protection system including a protection control unit, a detection unit, an account/password input unit, an ID acquiring unit, and an encryption unit is provided. The detection unit determines whether a storage device and a key storage device are both coupled to a host. The account/password input unit receives an administrator ID and an administrator password. The ID acquiring unit obtains IDs of the storage device and the key storage device. The encryption unit encrypts the administrator ID, the administrator password, and the IDs of the storage device and the key storage device into encryption data. The protection control unit stores the encryption data into the key storage device and sets an access mode of the storage device as a protection status according to the administrator ID and the administrator password. Thereby, the storage device can be effectively unlocked by using the key storage device.

Abstract: A memory storage device and a memory controller and an access method thereof are provided. The memory storage device includes a rewritable non-volatile memory chip having a plurality of physical blocks. The access method includes configuring a plurality of logical blocks to be mapped to a part of the physical blocks and dividing the logical blocks into at least a first partition and a second partition, wherein the first partition records an auto-execute file. The access method also includes determining whether a trigger signal is existent and sending a media ready message to a host system if the trigger signal is existent, so as to allow the host system to automatically run the auto-execute file and receive a first password. The access method further includes determining whether to provide the logical blocks in the second partition to the host system according to the first password received from the host system.