Abstract: a phase lock loop is disclosed, the phase lock loop comprising: a first phase detector configured to receive a first clock and a second clock and output a first detector output signal; a second phase detector configured to receive the first clock and the second clock and output a second detector output signal; a summing circuit to sum the first detector output signal and the second detector output signal into a control signal; a loop filter to filter the control signal into a refined control signal; and a controllable oscillator to generate the output clock in accordance with a control by the refined control signal.

Abstract: A method of performing frequency conversion and associated frequency converter are provided. The method includes: receiving an input signal and a plurality of periodic ternary signals of the same frequency but different timings; generating a plurality of conversion signals using a plurality of conversion paths in response to the input signal and states of said periodic ternary signals; and summing the conversion signals to generate an output signal.

Abstract: A high-speed continuous-time FIR (finite impulse response) filter comprises a plurality of processing cells configured in a cascade topology. Each processing cell receives a first signal and a second signal from a preceding circuit and a succeeding circuit, respectively, and outputs a third signal and a fourth signal to the succeeding circuit and the preceding circuit, respectively. Each processing cell further comprises a delay cell and a summing cell. Each of the delay cell and the summing cell performs a high speed signal processing using a combination of a feedback loop and a feedforward path.

Abstract: A broad-band active delay line comprises a plurality of broad-band active delay cells configured in a cascade topology. Each broad-band active delay cell comprises a feedback loop and a feedforward path to achieve a high bandwidth.

Abstract: An inter-stage gain of a conversion stage of a pipeline ADC is calibrated by imposing a perturbation to a sub-ADC within the conversion stage and adjusting a gain factor in a closed loop manner so as to make a conversion output substantially independent of the perturbation.

Abstract: In one embodiment, a phase error signal generated by a phase detector is equalized to compensate for the distortion in the phase error signal due to finite circuit speeds. The equalization may be based on suppressing the low frequency components of the phase error signal. For example, the amplitude of the phase error signal may be reduced when the amplitude of the phase error signal is not changing.

Abstract: An OFDM receiver includes a demodulator unit being coupled to a received signal for demodulating both an in-phase (I) component and a quadrature-phase (Q) component of the received signal; a serial to parallel unit for converting the output of the demodulator to a plurality of parallel paths, each path corresponding to a particular tone and having a plurality of time-domain samples; a fast Fourier transform circuit for generating frequency domain samples from the time-domain samples; and a equalization and I-Q mismatch correction circuit being coupled to the fast Fourier transform circuit for performing both frequency domain equalization and I-Q mismatch correction on at least one frequency domain sample being output by the fast Fourier transform circuit.

Abstract: A MCM (multi-carrier modulation) receiver that utilizes a plurality sub-carriers (e.g., tones) to transmit information in a frame-by-frame manner. Identify a first subset of sub-carriers that have negligible ISI (inter-symbol interference) and ICI (inter-carrier interference), and a second subset of sub-carriers that ISI/ICI cancellation is needed to improve the performance. For sub-carriers in the first subset, conventional equalization is performed to obtained soft decisions. For those sub-carriers in the second subset, perform ISI cancellation then ICI cancellation along with equalization. For sub-carriers in the second subset, identify a series of third subsets (one for each of the sub-carriers in the second subset) that cause interference to the sub-carriers in the second set. For sub-carriers in the third subset, identify a series of fourth subsets from a previous frame that cause interference to the sub-carriers in the third set.

Abstract: A wide-band adjustable gain low-noise amplifier (LNA) is disclosed. In various embodiments, the LNA includes a first inverting amplifier configured to generate a first intermediate signal. A first attenuator is configured to receive the first intermediate signal and to generate a second intermediate signal. In various embodiments, the LNA includes a second attenuator configured to generate a third intermediate signal. A second inverting amplifier is configured to generate a fourth intermediate signal using the third intermediate signal. A summing circuit is configured to generate an output signal based on the second and the fourth intermediate signals. Apparatus and methods according to various embodiments of the invention are also disclosed.

Abstract: A binary signal detection based on low resolution ADC includes: a variable-gain amplifier for amplifying an input signal with a gain factor controlled by a gain setting to generate an amplified signal; an ADC for converting the amplified signal into a converter output in accordance with a timing provided by a recovered clock, wherein the converter output has N levels; a timing detection circuit for generating a timing error signal based on the converter output; a filter for filtering the timing error signal to generate a control signal; a controllable oscillator for generating the recovered clock under a control of the control voltage; an automatic gain control for processing the converter data to set the gain setting to control the gain factor; and a data recovery circuit for generate a recovered data based on the converter output.

Abstract: A MCM (multi-carrier modulation) receiver that utilizes a plurality tones to transmit information. Identify a first subset of tones that have negligible ISI (inter-symbol interference) and ICI (inter-carrier interference), and a second subset of tones that ISI/ICI cancellation is needed to improve the performance. For tones in the first subset, conventional FEQ (frequency-domain equalization) is performed to obtained soft decisions from the raw decisions. For those tones in the second subset, perform FEQ along with ICI/ISI cancellation. For tones in the second subset, identify a third subset (one for each of the tones in the second subset) to perform ICI cancellation and a series of fourth subsets (one for each of the tones in the second subset) to perform ISI cancellation.

Abstract: A low flicker noise operational amplifier comprises two circuit branches of the same topology and a plurality of current source pairs. For each current source pair, the two current sources are commutatively steered into the two circuit branches via two sets of differential pair in a manner controlled by a pair of complementary logical signal.

Abstract: A method of performing frequency conversion and associated frequency converter are provided. The method includes: receiving an input signal and a plurality of periodic ternary signals of the same frequency but different timings; generating a plurality of conversion signals using a plurality of conversion paths in response to the input signal and states of said periodic ternary signals; and summing the conversion signals to generate an output signal.

Abstract: A multi-channel full-duplex transceiver is disclosed. The transceiver comprises: a clock generator for generating a first clock and a second clock based on a control code; a plurality of transmitters for transmitting a plurality of outgoing signals onto a plurality of channels, respectively; a plurality of receivers for receiving, sampling, and equalizing in parallel a plurality of incoming signals from said plurality of channels, respectively, to generate in parallel a plurality of equalized signals, respectively; a symbol-rate-converters for converting in parallel said equalized signals into a plurality of refined signals, respectively. In a first operation mode, the control code is established by detecting a timing difference between an output clock of the clock generator and a reference clock. In a second operation mode, the control code is established by detecting a timing embedded in one of said refined signals.

Abstract: A wide-band adjustable gain low-noise amplifier (LNA) is disclosed. In various embodiments, the LNA includes a first sub-circuit and a second sub-circuit coupled in parallel. In various embodiments, the first sub-circuit includes an amplifier configured to receive power when a logical signal is asserted and de-powered otherwise. In various embodiments, the second sub-circuit includes an amplifier configured to shunt an input node to a reference node using a resistor when the logical signal is de-asserted. Methods according to various embodiments of the invention are also disclosed.

Abstract: A time-to-digital converter (TDC) is disclosed, the TDC comprising: a plurality of parallel circuits for receiving a common first clock and for generating a plurality of delayed clocks; a plurality of sampling circuits for receiving and sampling said delayed clocks at an edge of a second clock to generate a plurality of decisions, respectively; and a decoder for receiving said decisions and for generating a digital output accordingly.

Abstract: A switch-capacitor loop filter is used to generate a control voltage for a voltage-controlled oscillator (VCO) in a phase lock loop (PLL). The switch-capacitor circuit works in a multi-phase manner including at least two non-overlapping phases: a sampling phase and a transfer phase. During the sampling phase, the current representing the phase difference between the reference clock and the feedback clock of the PLL is integrated by a sampling capacitor. During the transfer phase, the charge stored on the sampling capacitor is transferred to a load capacitor. The timing for controlling the switch-capacitor function is derived from the reference clock.

Abstract: A tri-state chopper (TSC) circuit and method is disclosed. The tri-state chopper (TSC) circuit receives an input signal and a ternary signal and generates an output signal, wherein: the output signal tracks the input signal in both magnitude and sign when the ternary signal is in a first state; the output signal tracks the input signal in magnitude but has an opposite sign when the ternary signal is in a second state; and the output signal is set to zero when the ternary signal is in a third state.

Abstract: A voltage controlled ring oscillator reduces sensitivity of an oscillation frequency to a control voltage by using a dual supply inverter logic circuit. The dual supply inverter logic circuit includes two inverter circuits coupled in parallel between an input terminal and an output terminal. The first inverter circuit is powered by a variable supply voltage while the second inverter circuit is powered by a substantially fixed supply voltage. The variable supply voltage serves as the control voltage for the voltage controlled ring oscillator and sets the oscillation frequency. The sensitivity of the oscillation frequency to changes in the variable supply voltage is reduced due to the parallel connection of the second inverter circuit powered by a different supply voltage.

Abstract: Apparatus and methods are provided for calibration within a delay chain. In various embodiments, such apparatus and techniques can be used to address delay mismatch, but are not limited to such applications. Additional apparatus, systems, and methods are disclosed.