Abstract: A dual-LO mixer is disclosed. The dual-LO mixer receives an input signal, a first reference signal of a first reference frequency, and a second reference signal of a second reference frequency, and performs a frequency translation to convert the input signal into an output signal, wherein the frequency difference between the input signal and the output signal is a sum or a difference of the first reference frequency and the second reference frequency.

Abstract: A hybrid circuit for a full-duplex transceiver includes a two-to-four wire ratio converter (50, Z1, Z2) for forwarding a transmitted signal TX? on a transmission line (41) in response to an input signal TX. The ratio converter also produces a signal RXA in response to a received signal RX arriving on the transmission line, wherein signal RXA includes an echo of input signal TX. A passive filter (H1) and a first active filter (H2) each filter input signal TX to generate signals TXA and TXB summed with the RXA signal to form a signal RXB at the input of an amplifier (52, Z3, Z4) producing an output signal RXC. A second active filter (H3) filters input signal TX to generate a signal TXC summed with the RXC signal to produce the output signal RX. The impedance of the passive filter is designed so that when the transmission line has a target impedance, such as the impedance of an ideal twisted pair, the TXA output signal of the passive filter adequately offsets the TX signal echo in RXA.

Abstract: A reference assisted control system and method thereof are disclosed. The method comprises: receiving a first input signal and a second control signal; generating a first intermediate signal in accordance with a difference between the first input signal and the first output signal; filtering the second control signal to generate a second intermediate signal; performing a weighted sum of the first intermediate signal and the second intermediate signal to generate the control signal; and outputting the first output signal in accordance with the control signal.

Abstract: Methods and apparatuses for alleviating charge leakage of VCO for phase lock loop are disclosed. The method comprises: receiving an input signal; generating an error signal representing a timing difference between the input signal and an output signal; filtering the error signal into a control signal; buffering the control signal into a buffered control signal; and generating the output signal in accordance with the buffered control signal. Buffering the control signal comprising using a high input resistance and low output resistance buffer circuit.

Abstract: An apparatus is disclosed, the apparatus comprising: a charge pump for receiving a phase signal representing a result of a phase detection and for outputting a current flowing between an internal node and an output node; a capacitive load shunt at the output node; a current source controlled by a bias voltage for outputting a compensation current to the internal node; a current sensor inserted between the internal node and the output node for sensing the current; and a feedback network for adjusting the bias voltage in accordance with an output of the current sensor.

Abstract: An apparatus is disclosed, the apparatus comprising: a charge pump for receiving a phase signal representing a result of a phase detection and for outputting a current flowing between an internal node and an output node; a capacitive load shunt at the output node; a current source controlled by a bias voltage for outputting a compensation current to the internal node; a current sensor inserted between the internal node and the output node for sensing the current; and a feedback network for adjusting the bias voltage in accordance with an output of the current sensor.

Abstract: An apparatus is disclosed, the apparatus comprising: a broad-band continuous-time adjustable weight summing cell for summing an input signal and a feedback signal into an intermediate signal in accordance with a weight factor for the feedback signal; a broad-band continuous-time delay cell for receiving the intermediate signal and outputting the feedback signal; a broad-band variable gain amplifier for amplifying the feedback signal into an output signal in accordance with a gain factor; and an adaptation circuit for adjusting the weight and the gain factor in accordance with the output signal and a timing defined by a clock signal so as to minimize an interference form a previous data to a present data embedded in the output signal.

Abstract: A method for reducing a phase noise in a digital fractional-N phase lock loop (PLL) is disclosed. The method comprises: quantifying a time difference between a reference clock and a feedback clock into a time difference signal; generating a residual error signal according to the time difference signal and an instantaneous error signal; filtering the residual error signal to generate a control code; controlling an oscillator using the control code to generate an output clock; receiving a fractional number between 0 and 1 to generate the instantaneous error signal; and dividing down the output clock by a divisor value according to the fractional number.

Abstract: A representative method of serial link transceiver without external reference clock is disclosed. The method includes: receiving an incoming signal; generating a local timing under control of a control code; generating a temperature sensor code by sensing a local temperature; generating a logical signal by detecting a presence of the incoming signal; adjusting the control code in a closed loop manner to make the local timing match that of the incoming signal and recording the control code and a value of the temperature sensor code as part of a template when the logical signal is asserted; and synthesizing the control code in accordance with the template when the logical signal is not asserted.

Abstract: A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit.

Abstract: A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic signals to a charge pump so that one of three values of current may be sourced to a loop filter, with the result that the circuit behaves as a conventional phase-locked loop having a fictitious divider circuit that is capable of dividing the output of the voltage-controlled oscillator by a non-integral value.

Abstract: The charge-pump apparatus is disclosed having a substantially fixed current source for outputting a first current of a first polarity; a variable current source for outputting a second current of a second polarity opposite to the first polarity; a first current steering network for steering the first current into either an output node or a termination node in accordance with a first control signal; a second current steering network for steering the second current into either the output node or the termination node in accordance with a second control signal; a voltage follower for receiving a first voltage associated with the output node and outputting a second voltage at an internal node; a current sensor inserted between the termination node and the internal node for sensing a current flowing between the termination node and the internal node; and a feedback network for adjusting the variable current source in accordance with an output of the current sensor.

Abstract: An apparatus comprises a charge pump to receive a phase signal representing a result of a phase detection and to output a current flowing between an internal node of the charge pump and an output node of the charge pump; a capacitive load coupled to the output node; a current source controlled by a bias voltage to output a compensation current to the output node; a current sensor coupled between the internal node and the output node to sense the current; and a feedback network to generate the bias voltage in accordance with an output of the current sensor. A comparable method is also disclosed.

Abstract: An interface circuit includes a plurality of receivers, a multiplexer, a plurality of shift registers and a latch circuit. Each of the receivers receives one of a plurality of sub-pixel values in one time period. The multiplexer multiplexes the sub-pixel values received by the receivers. The shift registers corresponds to the receivers, and each of the shift registers temporarily stores at least one of the multiplexed sub-pixel values. The latch circuit receives the sub-pixel values temporarily stored in the shift registers according to a shift register signal. Under a selection mode, a number of the receivers are turned on to receive the sub-pixel values and the rest of the receivers are turned off. A method for transmitting data through an interface circuit is also disclosed herein.

Abstract: A method and apparatus are provided for calibrating a ladder circuit. The apparatus includes: a logic unit for receiving a first logical signal, a second logical signal, and N control bits and for outputting N alternative control bits and an additional control bit, where N is an integer greater than 1; a core circuit for receiving the N alternative control bits, the additional control bit, and a tuning word, and for outputting an output signal, wherein the core circuit comprises N?1 series elements, N shunt elements with a connectivity controlled by the N alternative control bits, respectively, and a termination element with a connectivity controlled by the additional control bit; and a calibration circuit for receiving the first logical signal, the second logical signal, and the output signal and for outputting the tuning word.

Abstract: A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit.

Abstract: A direct conversion multi-band TV tuner includes: a plurality of RF (radio frequency) paths for processing the RF signal and for generating a plurality of processed RF signals, respectively; and a TSC (tri-state chopper) based quadrature frequency converter for receiving one of said processed RF signals and converting the received processed RF signal into a in-phase baseband signal and a quadrature baseband signals; wherein the TSC based quadrature frequency converter operates in accordance with a first set of periodic three-state control signals and a second set of periodic three-state control signals that are approximately 90 degrees offset from the first set of periodic three-state control signals.

Abstract: A driving circuit includes a receiving module, a data mapping module, a shift register module, a plurality of output channels, and a switching module. The receiving module receives data from a first number of parallel inputs. The data mapping module is coupled to the receiving module for mapping the data from the first number of parallel inputs to a second number of data buses according to a bus mode signal. The shift register module is used for generating a plurality of shift control signals. Each of the output channels latches data on the data buses based on the corresponding shift control signal. The switching module is connected between the shift register module and the output channels for outputting the shift control signals to the plurality of output channels according to the bus mode signal.

Abstract: An improved electric motor scooter includes: a front frame; a front wheel assembly coupled to the front frame and residing on a surface; a back frame; a back wheel assembly coupled to the back frame and residing on the surface; and a center pivot mechanism coupled to the front frame and the back frame. The center pivot mechanism includes a pivot and a folding axis around which the pivot rotates. The folding axis is not perpendicular to a longitudinal axis of the scooter and is tilted from the longitudinal axis at an angle. A rotation of the pivot in a direction folds the scooter vertically from the surface and moves the back wheel assembly toward the front wheel assembly according to the angle. During the folding, the front wheel assembly and the back wheel assembly each remains on the surface as the pivot rotates.

Abstract: A direct conversion method is disclosed. The method comprises: amplifying the input signal to generate an amplified signal; down-converting the amplified signal into two intermediate signals using a first set of ternary signals and a second set of ternary signals, respectively; filtering the first intermediate signal to generate a third intermediate signal; filtering the second intermediate signal to generate a fourth intermediate signal; digitizing the third intermediate signal into a first output signal in accordance with a first clock; digitizing the fourth intermediate signal into a second output signal in accordance with the first clock; and generating the first set of ternary signals and the second set of ternary signals based on a second clock.